static void ks_dw_pcie_msi_irq_ack(struct irq_data *d) { u32 offset, reg_offset, bit_pos; struct keystone_pcie *ks_pcie; unsigned int irq = d->irq; struct msi_desc *msi; struct pcie_port *pp; msi = irq_get_msi_desc(irq); pp = sys_to_pcie(msi->dev->bus->sysdata); ks_pcie = to_keystone_pcie(pp); offset = irq - irq_linear_revmap(pp->irq_domain, 0); update_reg_offset_bit_pos(offset, ®_offset, &bit_pos); writel(BIT(bit_pos), ks_pcie->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4)); writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI); }
static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata); int ret; if ((size == 2) && (where & 1)) return PCIBIOS_BAD_REGISTER_NUMBER; else if ((size == 4) && (where & 3)) return PCIBIOS_BAD_REGISTER_NUMBER; ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ, bus, devfn, where, val); if (ret != PCIBIOS_SUCCESSFUL) { *val = 0xffffffff; return ret; } if (size == 1) *val = (*val >> (8 * (where & 3))) & 0xff; else if (size == 2)
static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d) { struct keystone_pcie *ks_pcie; unsigned int irq = d->irq; struct msi_desc *msi; struct pcie_port *pp; u32 offset; msi = irq_get_msi_desc(irq); pp = sys_to_pcie(msi->dev->bus->sysdata); ks_pcie = to_keystone_pcie(pp); offset = irq - irq_linear_revmap(pp->irq_domain, 0); /* Mask the end point if PVM implemented */ if (IS_ENABLED(CONFIG_PCI_MSI)) { if (msi->msi_attrib.maskbit) pci_msi_unmask_irq(d); } ks_dw_pcie_msi_set_irq(pp, offset); }