static void macio_newworld_realize(PCIDevice *d, Error **errp)
{
MacIOState *s = MACIO(d);
NewWorldMacIOState *ns = NEWWORLD_MACIO(d);
Error *err = NULL;
SysBusDevice *sysbus_dev;
MemoryRegion *timer_memory = NULL;
int i;
int cur_irq = 0;
macio_common_realize(d, &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
sysbus_connect_irq(sysbus_dev, 0, ns->irqs[cur_irq++]);
sysbus_dev = SYS_BUS_DEVICE(&s->escc);
sysbus_connect_irq(sysbus_dev, 0, ns->irqs[cur_irq++]);
sysbus_connect_irq(sysbus_dev, 1, ns->irqs[cur_irq++]);
/* OpenPIC */
sysbus_dev = SYS_BUS_DEVICE(ns->pic);
memory_region_add_subregion(&s->bar, 0x40000,
sysbus_mmio_get_region(sysbus_dev, 0));
/* IDE buses */
for (i = 0; i < ARRAY_SIZE(ns->ide); i++) {
qemu_irq irq0 = ns->irqs[cur_irq++];
qemu_irq irq1 = ns->irqs[cur_irq++];
macio_realize_ide(s, &ns->ide[i], irq0, irq1, 0x16 + (i * 4), &err);
if (err) {
error_propagate(errp, err);
return;
}
}
/* Timer */
timer_memory = g_new(MemoryRegion, 1);
memory_region_init_io(timer_memory, OBJECT(s), &timer_ops, NULL, "timer",
0x1000);
memory_region_add_subregion(&s->bar, 0x15000, timer_memory);
}
static void macio_oldworld_realize(PCIDevice *d, Error **errp)
{
MacIOState *s = MACIO(d);
OldWorldMacIOState *os = OLDWORLD_MACIO(d);
Error *err = NULL;
SysBusDevice *sysbus_dev;
int i;
int cur_irq = 0;
macio_common_realize(d, &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]);
object_property_set_bool(OBJECT(&os->nvram), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_dev = SYS_BUS_DEVICE(&os->nvram);
memory_region_add_subregion(&s->bar, 0x60000,
sysbus_mmio_get_region(sysbus_dev, 0));
pmac_format_nvram_partition(&os->nvram, os->nvram.size);
if (s->pic_mem) {
/* Heathrow PIC */
memory_region_add_subregion(&s->bar, 0x00000, s->pic_mem);
}
/* IDE buses */
for (i = 0; i < ARRAY_SIZE(os->ide); i++) {
qemu_irq irq0 = os->irqs[cur_irq++];
qemu_irq irq1 = os->irqs[cur_irq++];
macio_realize_ide(s, &os->ide[i], irq0, irq1, 0x16 + (i * 4), &err);
if (err) {
error_propagate(errp, err);
return;
}
}
}
static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
const char *name, hwaddr size)
{
SysBusDevice *s;
NICInfo *nd = &nd_table[0];
/* In hardware this is a LAN9220; the LAN9118 is software compatible
* except that it doesn't support the checksum-offload feature.
*/
qemu_check_nic_model(nd, "lan9118");
mms->lan9118 = qdev_create(NULL, "lan9118");
qdev_set_nic_properties(mms->lan9118, nd);
qdev_init_nofail(mms->lan9118);
s = SYS_BUS_DEVICE(mms->lan9118);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16));
return sysbus_mmio_get_region(s, 0);
}
static int macio_oldworld_initfn(PCIDevice *d)
{
MacIOState *s = MACIO(d);
OldWorldMacIOState *os = OLDWORLD_MACIO(d);
SysBusDevice *sysbus_dev;
int i;
int cur_irq = 0;
int ret = macio_common_initfn(d);
if (ret < 0) {
return ret;
}
sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]);
ret = qdev_init(DEVICE(&os->nvram));
if (ret < 0) {
return ret;
}
sysbus_dev = SYS_BUS_DEVICE(&os->nvram);
memory_region_add_subregion(&s->bar, 0x60000,
sysbus_mmio_get_region(sysbus_dev, 0));
pmac_format_nvram_partition(&os->nvram, os->nvram.size);
if (s->pic_mem) {
/* Heathrow PIC */
memory_region_add_subregion(&s->bar, 0x00000, s->pic_mem);
}
/* IDE buses */
for (i = 0; i < ARRAY_SIZE(os->ide); i++) {
qemu_irq irq0 = os->irqs[cur_irq++];
qemu_irq irq1 = os->irqs[cur_irq++];
ret = macio_initfn_ide(s, &os->ide[i], irq0, irq1, 0x16 + (i * 4));
if (ret < 0) {
return ret;
}
}
return 0;
}
static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
const LxBoardDesc *board,
DriveInfo *dinfo, int be)
{
SysBusDevice *s;
DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
&error_abort);
qdev_prop_set_uint32(dev, "num-blocks",
board->flash_size / board->flash_sector_size);
qdev_prop_set_uint64(dev, "sector-length", board->flash_sector_size);
qdev_prop_set_uint8(dev, "width", 4);
qdev_prop_set_bit(dev, "big-endian", be);
qdev_prop_set_string(dev, "name", "lx60.io.flash");
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
memory_region_add_subregion(address_space, board->flash_base,
sysbus_mmio_get_region(s, 0));
return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
}
static int macio_common_initfn(PCIDevice *d)
{
MacIOState *s = MACIO(d);
SysBusDevice *sysbus_dev;
int ret;
d->config[0x3d] = 0x01; // interrupt on pin 1
ret = qdev_init(DEVICE(&s->cuda));
if (ret < 0) {
return ret;
}
sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
memory_region_add_subregion(&s->bar, 0x16000,
sysbus_mmio_get_region(sysbus_dev, 0));
macio_bar_setup(s);
pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar);
return 0;
}
static void create_virtio_regions(VersalVirt *s)
{
int virtio_mmio_size = 0x200;
int i;
for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
char *name = g_strdup_printf("virtio%d", i);;
hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
int irq = VERSAL_RSVD_IRQ_FIRST + i;
MemoryRegion *mr;
DeviceState *dev;
qemu_irq pic_irq;
pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
dev = qdev_create(NULL, "virtio-mmio");
object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev),
&error_fatal);
qdev_init_nofail(dev);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->soc.mr_ps, base, mr);
g_free(name);
}
for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
int irq = VERSAL_RSVD_IRQ_FIRST + i;
char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0);
qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
GIC_FDT_IRQ_TYPE_SPI, irq,
GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
2, base, 2, virtio_mmio_size);
qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio");
g_free(name);
}
}
static void macio_common_realize(PCIDevice *d, Error **errp)
{
MacIOState *s = MACIO(d);
SysBusDevice *sysbus_dev;
Error *err = NULL;
MemoryRegion *dbdma_mem;
s->dbdma = DBDMA_init(&dbdma_mem);
memory_region_add_subregion(&s->bar, 0x08000, dbdma_mem);
object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
memory_region_add_subregion(&s->bar, 0x16000,
sysbus_mmio_get_region(sysbus_dev, 0));
macio_bar_setup(s);
pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar);
}
static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
const char *name, hwaddr size)
{
/*
* The AN505 has five PL022 SPI controllers.
* One of these should have the LCD controller behind it; the others
* are connected only to the FPGA's "general purpose SPI connector"
* or "shield" expansion connectors.
* Note that if we do implement devices behind SPI, the chip select
* lines are set via the "MISC" register in the MPS2 FPGAIO device.
*/
PL022State *spi = opaque;
int i = spi - &mms->spi[0];
SysBusDevice *s;
sysbus_init_child_obj(OBJECT(mms), name, spi, sizeof(mms->spi[0]),
TYPE_PL022);
object_property_set_bool(OBJECT(spi), true, "realized", &error_fatal);
s = SYS_BUS_DEVICE(spi);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i));
return sysbus_mmio_get_region(s, 0);
}
static int macio_oldworld_initfn(PCIDevice *d)
{
MacIOState *s = MACIO(d);
OldWorldMacIOState *os = OLDWORLD_MACIO(d);
SysBusDevice *sysbus_dev;
int ret = macio_common_initfn(d);
if (ret < 0) {
return ret;
}
sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
sysbus_connect_irq(sysbus_dev, 0, os->irqs[0]);
ret = qdev_init(DEVICE(&os->nvram));
if (ret < 0) {
return ret;
}
sysbus_dev = SYS_BUS_DEVICE(&os->nvram);
memory_region_add_subregion(&s->bar, 0x60000,
sysbus_mmio_get_region(sysbus_dev, 0));
pmac_format_nvram_partition(&os->nvram, os->nvram.size);
if (s->pic_mem) {
/* Heathrow PIC */
memory_region_add_subregion(&s->bar, 0x00000, s->pic_mem);
}
sysbus_dev = SYS_BUS_DEVICE(&os->ide);
sysbus_connect_irq(sysbus_dev, 0, os->irqs[1]);
sysbus_connect_irq(sysbus_dev, 1, os->irqs[2]);
macio_ide_register_dma(&os->ide, s->dbdma, 0x16);
ret = qdev_init(DEVICE(&os->ide));
if (ret < 0) {
return ret;
}
return 0;
}
static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
const char *name, hwaddr size)
{
CMSDKAPBUART *uart = opaque;
int i = uart - &mms->uart[0];
int rxirqno = i * 2;
int txirqno = i * 2 + 1;
int combirqno = i + 10;
SysBusDevice *s;
DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),
TYPE_CMSDK_APB_UART);
qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);
object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
s = SYS_BUS_DEVICE(uart);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno));
sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno));
sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno));
return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);
}
static void sun4uv_init(MemoryRegion *address_space_mem,
MachineState *machine,
const struct hwdef *hwdef)
{
SPARCCPU *cpu;
Nvram *nvram;
unsigned int i;
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
SabreState *sabre;
PCIBus *pci_bus, *pci_busA, *pci_busB;
PCIDevice *ebus, *pci_dev;
SysBusDevice *s;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DeviceState *iommu, *dev;
FWCfgState *fw_cfg;
NICInfo *nd;
MACAddr macaddr;
bool onboard_nic;
/* init CPUs */
cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
/* IOMMU */
iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
qdev_init_nofail(iommu);
/* set up devices */
ram_init(0, machine->ram_size);
prom_init(hwdef->prom_addr, bios_name);
/* Init sabre (PCI host bridge) */
sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
&error_abort);
qdev_init_nofail(DEVICE(sabre));
/* Wire up PCI interrupts to CPU */
for (i = 0; i < IVEC_MAX; i++) {
qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
}
pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
/* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
reserved (leaving no slots free after on-board devices) however slots
0-3 are free on busB */
pci_bus->slot_reserved_mask = 0xfffffffc;
pci_busA->slot_reserved_mask = 0xfffffff1;
pci_busB->slot_reserved_mask = 0xfffffff0;
ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
hwdef->console_serial_base);
qdev_init_nofail(DEVICE(ebus));
/* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
memset(&macaddr, 0, sizeof(MACAddr));
onboard_nic = false;
for (i = 0; i < nb_nics; i++) {
nd = &nd_table[i];
if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
if (!onboard_nic) {
pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
true, "sunhme");
memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
onboard_nic = true;
} else {
pci_dev = pci_create(pci_busB, -1, "sunhme");
}
} else {
pci_dev = pci_create(pci_busB, -1, nd->model);
}
dev = &pci_dev->qdev;
qdev_set_nic_properties(dev, nd);
qdev_init_nofail(dev);
}
/* If we don't have an onboard NIC, grab a default MAC address so that
* we have a valid machine id */
if (!onboard_nic) {
qemu_macaddr_default_if_unset(&macaddr);
}
ide_drive_get(hd, ARRAY_SIZE(hd));
pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
qdev_init_nofail(&pci_dev->qdev);
pci_ide_create_devs(pci_dev, hd);
/* Map NVRAM into I/O (ebus) space */
nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
s = SYS_BUS_DEVICE(nvram);
memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
sysbus_mmio_get_region(s, 0));
initrd_size = 0;
initrd_addr = 0;
kernel_size = sun4u_load_kernel(machine->kernel_filename,
machine->initrd_filename,
ram_size, &initrd_size, &initrd_addr,
&kernel_addr, &kernel_entry);
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
machine->boot_order,
kernel_addr, kernel_size,
machine->kernel_cmdline,
initrd_addr, initrd_size,
/* XXX: need an option to load a NVRAM image */
0,
graphic_width, graphic_height, graphic_depth,
(uint8_t *)&macaddr);
dev = qdev_create(NULL, TYPE_FW_CFG_IO);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
qdev_init_nofail(dev);
memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
&FW_CFG_IO(dev)->comb_iomem);
fw_cfg = FW_CFG(dev);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (machine->kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
strlen(machine->kernel_cmdline) + 1);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
}
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
/* EBUS (Eight bit bus) bridge */
static void ebus_realize(PCIDevice *pci_dev, Error **errp)
{
EbusState *s = EBUS(pci_dev);
SysBusDevice *sbd;
DeviceState *dev;
qemu_irq *isa_irq;
DriveInfo *fd[MAX_FD];
int i;
s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
pci_address_space_io(pci_dev), errp);
if (!s->isa_bus) {
error_setg(errp, "unable to instantiate EBUS ISA bus");
return;
}
/* ISA bus */
isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
isa_bus_irqs(s->isa_bus, isa_irq);
qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
ISA_NUM_IRQS);
/* Serial ports */
i = 0;
if (s->console_serial_base) {
serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
i++;
}
serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS);
/* Parallel ports */
parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
/* Keyboard */
isa_create_simple(s->isa_bus, "i8042");
/* Floppy */
for (i = 0; i < MAX_FD; i++) {
fd[i] = drive_get(IF_FLOPPY, 0, i);
}
dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
if (fd[0]) {
qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
&error_abort);
}
if (fd[1]) {
qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
&error_abort);
}
qdev_prop_set_uint32(dev, "dma", -1);
qdev_init_nofail(dev);
/* Power */
dev = qdev_create(NULL, TYPE_SUN4U_POWER);
qdev_init_nofail(dev);
sbd = SYS_BUS_DEVICE(dev);
memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
sysbus_mmio_get_region(sbd, 0));
/* PCI */
pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
pci_dev->config[0x05] = 0x00;
pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
pci_dev->config[0x07] = 0x03; // status = medium devsel
pci_dev->config[0x09] = 0x00; // programming i/f
pci_dev->config[0x0D] = 0x0a; // latency_timer
memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
0, 0x1000000);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
0, 0x8000);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
}
/* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
const char *boot_device = machine->boot_order;
Core99MachineState *core99_machine = CORE99_MACHINE(machine);
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
char *filename;
IrqLines *openpic_irqs;
int linux_boot, i, j, k;
MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
hwaddr kernel_base, initrd_base, cmdline_base = 0;
long kernel_size, initrd_size;
UNINHostState *uninorth_pci;
PCIBus *pci_bus;
NewWorldMacIOState *macio;
bool has_pmu, has_adb;
MACIOIDEState *macio_ide;
BusState *adb_bus;
MacIONVRAMState *nvr;
int bios_size;
int ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
void *fw_cfg;
int machine_arch;
SysBusDevice *s;
DeviceState *dev, *pic_dev;
hwaddr nvram_addr = 0xFFF04000;
uint64_t tbfreq;
linux_boot = (kernel_filename != NULL);
/* init CPUs */
for (i = 0; i < smp_cpus; i++) {
cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, TBFREQ);
qemu_register_reset(ppc_core99_reset, cpu);
}
/* allocate RAM */
memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size);
memory_region_add_subregion(get_system_memory(), 0, ram);
/* allocate and load BIOS */
memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE,
&error_fatal);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
/* Load OpenBIOS (ELF) */
if (filename) {
bios_size = load_elf(filename, NULL, NULL, NULL,
NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
g_free(filename);
} else {
bios_size = -1;
}
if (bios_size < 0 || bios_size > BIOS_SIZE) {
error_report("could not load PowerPC bios '%s'", bios_name);
exit(1);
}
if (linux_boot) {
uint64_t lowaddr = 0;
int bswap_needed;
#ifdef BSWAP_NEEDED
bswap_needed = 1;
#else
bswap_needed = 0;
#endif
kernel_base = KERNEL_LOAD_ADDR;
kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
0, 0);
if (kernel_size < 0)
kernel_size = load_aout(kernel_filename, kernel_base,
ram_size - kernel_base, bswap_needed,
TARGET_PAGE_SIZE);
if (kernel_size < 0)
kernel_size = load_image_targphys(kernel_filename,
kernel_base,
ram_size - kernel_base);
if (kernel_size < 0) {
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
}
/* load initrd */
if (initrd_filename) {
initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
initrd_size = load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
if (initrd_size < 0) {
error_report("could not load initial ram disk '%s'",
initrd_filename);
exit(1);
}
cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
} else {
initrd_base = 0;
initrd_size = 0;
cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
}
ppc_boot_device = 'm';
} else {
kernel_base = 0;
kernel_size = 0;
initrd_base = 0;
initrd_size = 0;
ppc_boot_device = '\0';
/* We consider that NewWorld PowerMac never have any floppy drive
* For now, OHW cannot boot from the network.
*/
for (i = 0; boot_device[i] != '\0'; i++) {
if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
ppc_boot_device = boot_device[i];
break;
}
}
if (ppc_boot_device == '\0') {
error_report("No valid boot device for Mac99 machine");
exit(1);
}
}
/* UniN init */
dev = qdev_create(NULL, TYPE_UNI_NORTH);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
memory_region_add_subregion(get_system_memory(), 0xf8000000,
sysbus_mmio_get_region(s, 0));
openpic_irqs = g_new0(IrqLines, smp_cpus);
for (i = 0; i < smp_cpus; i++) {
/* Mac99 IRQ connection between OpenPIC outputs pins
* and PowerPC input pins
*/
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_6xx:
openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
/* Not connected ? */
openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
/* Check this */
openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
break;
#if defined(TARGET_PPC64)
case PPC_FLAGS_INPUT_970:
openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
/* Not connected ? */
openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
/* Check this */
openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
break;
#endif /* defined(TARGET_PPC64) */
default:
error_report("Bus model not supported on mac99 machine");
exit(1);
}
}
pic_dev = qdev_create(NULL, TYPE_OPENPIC);
qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO);
qdev_init_nofail(pic_dev);
s = SYS_BUS_DEVICE(pic_dev);
k = 0;
for (i = 0; i < smp_cpus; i++) {
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]);
}
}
g_free(openpic_irqs);
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */
/* Uninorth AGP bus */
dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
qdev_init_nofail(dev);
uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
s = SYS_BUS_DEVICE(dev);
/* PCI hole */
memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
sysbus_mmio_get_region(s, 2));
/* Register 8 MB of ISA IO space */
memory_region_add_subregion(get_system_memory(), 0xf2000000,
sysbus_mmio_get_region(s, 3));
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
machine_arch = ARCH_MAC99_U3;
} else {
/* Use values found on a real PowerMac */
/* Uninorth AGP bus */
dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
/* Uninorth internal bus */
dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, 0xf4800000);
sysbus_mmio_map(s, 1, 0xf4c00000);
/* Uninorth main bus */
dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
qdev_init_nofail(dev);
uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
s = SYS_BUS_DEVICE(dev);
/* PCI hole */
memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
sysbus_mmio_get_region(s, 2));
/* Register 8 MB of ISA IO space */
memory_region_add_subregion(get_system_memory(), 0xf2000000,
sysbus_mmio_get_region(s, 3));
sysbus_mmio_map(s, 0, 0xf2800000);
sysbus_mmio_map(s, 1, 0xf2c00000);
machine_arch = ARCH_MAC99;
}
machine->usb |= defaults_enabled() && !machine->usb_disabled;
has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA);
has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA ||
core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB);
/* Timebase Frequency */
if (kvm_enabled()) {
tbfreq = kvmppc_get_tbfreq();
} else {
tbfreq = TBFREQ;
}
/* init basic PC hardware */
pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus;
/* MacIO */
macio = NEWWORLD_MACIO(pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO));
dev = DEVICE(macio);
qdev_prop_set_uint64(dev, "frequency", tbfreq);
qdev_prop_set_bit(dev, "has-pmu", has_pmu);
qdev_prop_set_bit(dev, "has-adb", has_adb);
object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic",
&error_abort);
qdev_init_nofail(dev);
/* We only emulate 2 out of 3 IDE controllers for now */
ide_drive_get(hd, ARRAY_SIZE(hd));
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[0]"));
macio_ide_init_drives(macio_ide, hd);
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[1]"));
macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
if (has_adb) {
if (has_pmu) {
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pmu"));
} else {
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
}
adb_bus = qdev_get_child_bus(dev, "adb.0");
dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true);
qdev_init_nofail(dev);
dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true);
qdev_init_nofail(dev);
}
if (machine->usb) {
pci_create_simple(pci_bus, -1, "pci-ohci");
/* U3 needs to use USB for input because Linux doesn't support via-cuda
on PPC64 */
if (!has_adb || machine_arch == ARCH_MAC99_U3) {
USBBus *usb_bus = usb_bus_find(-1);
usb_create_simple(usb_bus, "usb-kbd");
usb_create_simple(usb_bus, "usb-mouse");
}
}
pci_vga_init(pci_bus);
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) {
graphic_depth = 15;
}
for (i = 0; i < nb_nics; i++) {
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
}
/* The NewWorld NVRAM is not located in the MacIO device */
#ifdef CONFIG_KVM
if (kvm_enabled() && getpagesize() > 4096) {
/* We can't combine read-write and read-only in a single page, so
move the NVRAM out of ROM again for KVM */
nvram_addr = 0xFFE00000;
}
#endif
dev = qdev_create(NULL, TYPE_MACIO_NVRAM);
qdev_prop_set_uint32(dev, "size", 0x2000);
qdev_prop_set_uint32(dev, "it_shift", 1);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
nvr = MACIO_NVRAM(dev);
pmac_format_nvram_partition(nvr, 0x2000);
/* No PCI init: the BIOS will do it */
dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg), NULL);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
if (kvm_enabled()) {
#ifdef CONFIG_KVM
uint8_t *hypercall;
hypercall = g_malloc(16);
kvmppc_get_hypercall(env, hypercall, 16);
fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
#endif
}
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
/* Mac OS X requires a "known good" clock-frequency value; pass it one. */
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr);
/* MacOS NDRV VGA driver */
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
if (filename) {
gchar *ndrv_file;
gsize ndrv_size;
if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
}
g_free(filename);
}
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
static void mips_cps_realize(DeviceState *dev, Error **errp)
{
MIPSCPSState *s = MIPS_CPS(dev);
CPUMIPSState *env;
MIPSCPU *cpu;
int i;
Error *err = NULL;
target_ulong gcr_base;
bool itu_present = false;
bool saar_present = false;
for (i = 0; i < s->num_vp; i++) {
cpu = MIPS_CPU(cpu_create(s->cpu_type));
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
cpu_mips_clock_init(cpu);
env = &cpu->env;
if (cpu_mips_itu_supported(env)) {
itu_present = true;
/* Attach ITC Tag to the VP */
env->itc_tag = mips_itu_get_tag_region(&s->itu);
env->itu = &s->itu;
}
qemu_register_reset(main_cpu_reset, cpu);
}
cpu = MIPS_CPU(first_cpu);
env = &cpu->env;
saar_present = (bool)env->saarp;
/* Inter-Thread Communication Unit */
if (itu_present) {
object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU);
qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default());
object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present",
&err);
if (saar_present) {
qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_SAAR);
}
object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
}
/* Cluster Power Controller */
object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC);
qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default());
object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err);
object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
/* Global Interrupt Controller */
object_initialize(&s->gic, sizeof(s->gic), TYPE_MIPS_GIC);
qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err);
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
/* Global Configuration Registers */
gcr_base = env->CP0_CMGCRBase << 4;
object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR);
qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default());
object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err);
object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err);
object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->container, gcr_base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
}
static void a9mp_priv_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
A9MPPrivState *s = A9MPCORE_PRIV(dev);
DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev;
SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev,
*wdtbusdev;
Error *err = NULL;
int i;
bool has_el3;
Object *cpuobj;
scudev = DEVICE(&s->scu);
qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
scubusdev = SYS_BUS_DEVICE(&s->scu);
gicdev = DEVICE(&s->gic);
qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
/* Make the GIC's TZ support match the CPUs. We assume that
* either all the CPUs have TZ, or none do.
*/
cpuobj = OBJECT(qemu_get_cpu(0));
has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
object_property_get_bool(cpuobj, "has_el3", &error_abort);
qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
gicbusdev = SYS_BUS_DEVICE(&s->gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(sbd, gicbusdev);
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32);
gtimerdev = DEVICE(&s->gtimer);
qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer);
mptimerdev = DEVICE(&s->mptimer);
qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer);
wdtdev = DEVICE(&s->wdt);
qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
wdtbusdev = SYS_BUS_DEVICE(&s->wdt);
/* Memory map (addresses are offsets from PERIPHBASE):
* 0x0000-0x00ff -- Snoop Control Unit
* 0x0100-0x01ff -- GIC CPU interface
* 0x0200-0x02ff -- Global Timer
* 0x0300-0x05ff -- nothing
* 0x0600-0x06ff -- private timers and watchdogs
* 0x0700-0x0fff -- nothing
* 0x1000-0x1fff -- GIC Distributor
*/
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(scubusdev, 0));
/* GIC CPU interface */
memory_region_add_subregion(&s->container, 0x100,
sysbus_mmio_get_region(gicbusdev, 1));
memory_region_add_subregion(&s->container, 0x200,
sysbus_mmio_get_region(gtimerbusdev, 0));
/* Note that the A9 exposes only the "timer/watchdog for this core"
* memory region, not the "timer/watchdog for core X" ones 11MPcore has.
*/
memory_region_add_subregion(&s->container, 0x600,
sysbus_mmio_get_region(mptimerbusdev, 0));
memory_region_add_subregion(&s->container, 0x620,
sysbus_mmio_get_region(wdtbusdev, 0));
memory_region_add_subregion(&s->container, 0x1000,
sysbus_mmio_get_region(gicbusdev, 0));
/* Wire up the interrupt from each watchdog and timer.
* For each core the global timer is PPI 27, the private
* timer is PPI 29 and the watchdog PPI 30.
*/
for (i = 0; i < s->num_cpu; i++) {
int ppibase = (s->num_irq - 32) + i * 32;
sysbus_connect_irq(gtimerbusdev, i,
qdev_get_gpio_in(gicdev, ppibase + 27));
sysbus_connect_irq(mptimerbusdev, i,
qdev_get_gpio_in(gicdev, ppibase + 29));
sysbus_connect_irq(wdtbusdev, i,
qdev_get_gpio_in(gicdev, ppibase + 30));
}
}
static void ppc_heathrow_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
const char *boot_device = machine->boot_order;
MemoryRegion *sysmem = get_system_memory();
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
char *filename;
int linux_boot, i;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
uint32_t kernel_base, initrd_base, cmdline_base = 0;
int32_t kernel_size, initrd_size;
PCIBus *pci_bus;
OldWorldMacIOState *macio;
MACIOIDEState *macio_ide;
SysBusDevice *s;
DeviceState *dev, *pic_dev;
BusState *adb_bus;
int bios_size;
uint16_t ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
void *fw_cfg;
uint64_t tbfreq;
linux_boot = (kernel_filename != NULL);
/* init CPUs */
for (i = 0; i < smp_cpus; i++) {
cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
/* Set time-base frequency to 16.6 Mhz */
cpu_ppc_tb_init(env, TBFREQ);
qemu_register_reset(ppc_heathrow_reset, cpu);
}
/* allocate RAM */
if (ram_size > 2047 * MiB) {
error_report("Too much memory for this machine: %" PRId64 " MB, "
"maximum 2047 MB", ram_size / MiB);
exit(1);
}
memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram",
ram_size);
memory_region_add_subregion(sysmem, 0, ram);
/* allocate and load BIOS */
memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
&error_fatal);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(sysmem, PROM_ADDR, bios);
/* Load OpenBIOS (ELF) */
if (filename) {
bios_size = load_elf(filename, NULL, 0, NULL, NULL, NULL, NULL,
1, PPC_ELF_MACHINE, 0, 0);
g_free(filename);
} else {
bios_size = -1;
}
if (bios_size < 0 || bios_size > BIOS_SIZE) {
error_report("could not load PowerPC bios '%s'", bios_name);
exit(1);
}
if (linux_boot) {
uint64_t lowaddr = 0;
int bswap_needed;
#ifdef BSWAP_NEEDED
bswap_needed = 1;
#else
bswap_needed = 0;
#endif
kernel_base = KERNEL_LOAD_ADDR;
kernel_size = load_elf(kernel_filename, NULL,
translate_kernel_address, NULL,
NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
0, 0);
if (kernel_size < 0)
kernel_size = load_aout(kernel_filename, kernel_base,
ram_size - kernel_base, bswap_needed,
TARGET_PAGE_SIZE);
if (kernel_size < 0)
kernel_size = load_image_targphys(kernel_filename,
kernel_base,
ram_size - kernel_base);
if (kernel_size < 0) {
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
}
/* load initrd */
if (initrd_filename) {
initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
initrd_size = load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
if (initrd_size < 0) {
error_report("could not load initial ram disk '%s'",
initrd_filename);
exit(1);
}
cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
} else {
initrd_base = 0;
initrd_size = 0;
cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
}
ppc_boot_device = 'm';
} else {
kernel_base = 0;
kernel_size = 0;
initrd_base = 0;
initrd_size = 0;
ppc_boot_device = '\0';
for (i = 0; boot_device[i] != '\0'; i++) {
/* TOFIX: for now, the second IDE channel is not properly
* used by OHW. The Mac floppy disk are not emulated.
* For now, OHW cannot boot from the network.
*/
#if 0
if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
ppc_boot_device = boot_device[i];
break;
}
#else
if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
ppc_boot_device = boot_device[i];
break;
}
#endif
}
if (ppc_boot_device == '\0') {
error_report("No valid boot device for G3 Beige machine");
exit(1);
}
}
/* XXX: we register only 1 output pin for heathrow PIC */
pic_dev = qdev_create(NULL, TYPE_HEATHROW);
qdev_init_nofail(pic_dev);
/* Connect the heathrow PIC outputs to the 6xx bus */
for (i = 0; i < smp_cpus; i++) {
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_6xx:
qdev_connect_gpio_out(pic_dev, 0,
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
break;
default:
error_report("Bus model not supported on OldWorld Mac machine");
exit(1);
}
}
/* Timebase Frequency */
if (kvm_enabled()) {
tbfreq = kvmppc_get_tbfreq();
} else {
tbfreq = TBFREQ;
}
/* init basic PC hardware */
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
error_report("Only 6xx bus is supported on heathrow machine");
exit(1);
}
/* Grackle PCI host bridge */
dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, GRACKLE_BASE);
sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
/* PCI hole */
memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
sysbus_mmio_get_region(s, 2));
/* Register 2 MB of ISA IO space */
memory_region_add_subregion(get_system_memory(), 0xfe000000,
sysbus_mmio_get_region(s, 3));
pci_bus = PCI_HOST_BRIDGE(dev)->bus;
pci_vga_init(pci_bus);
for (i = 0; i < nb_nics; i++) {
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
}
ide_drive_get(hd, ARRAY_SIZE(hd));
/* MacIO */
macio = OLDWORLD_MACIO(pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO));
dev = DEVICE(macio);
qdev_prop_set_uint64(dev, "frequency", tbfreq);
object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic",
&error_abort);
qdev_init_nofail(dev);
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[0]"));
macio_ide_init_drives(macio_ide, hd);
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[1]"));
macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
adb_bus = qdev_get_child_bus(dev, "adb.0");
dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
qdev_init_nofail(dev);
dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
qdev_init_nofail(dev);
if (machine_usb(machine)) {
pci_create_simple(pci_bus, -1, "pci-ohci");
}
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
graphic_depth = 15;
/* No PCI init: the BIOS will do it */
dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg), NULL);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
if (kvm_enabled()) {
#ifdef CONFIG_KVM
uint8_t *hypercall;
hypercall = g_malloc(16);
kvmppc_get_hypercall(env, hypercall, 16);
fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
#endif
}
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
/* Mac OS X requires a "known good" clock-frequency value; pass it one. */
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
/* MacOS NDRV VGA driver */
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
if (filename) {
gchar *ndrv_file;
gsize ndrv_size;
if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
}
g_free(filename);
}
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
static void reptar_init(MachineState *machine)
{
MemoryRegion *sysmem = get_system_memory();
struct reptar_s *s = (struct reptar_s *)g_malloc0(sizeof(*s));
DriveInfo *dmtd = NULL, *dsd = NULL, *pflash = NULL;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
/* (DRE) */
uint32_t pflash_size = 16 << 10; /* 16 KB */
if (ram_size > 1024 * 1024 * 1024) {
fprintf(stderr, "reptar: maximum permitted RAM size 1024MB\n");
exit(1);
}
/* Check if we are in -kernel u-boot.bin mode */
if (kernel_filename) {
/* (DRE) We do the following in order to retrieve the kernel filename during the boot process.
* For example, if qemu was launched with -kernel u-boot.bin */
reptar_binfo.ram_size = ram_size;
reptar_binfo.kernel_filename = kernel_filename;
reptar_binfo.kernel_cmdline = kernel_cmdline;
reptar_binfo.initrd_filename = initrd_filename;
reptar_binfo.loader_start = 0x40014100; /* Start of small bootloader*/
reptar_binfo.board_id = 0;
} else
reptar_binfo.kernel_filename = NULL;
s->cpu = omap3_mpu_init(sysmem, omap3430, ram_size, NULL, NULL, serial_hds[0], NULL);
pflash = drive_get(IF_PFLASH, 0, 0);
if (pflash) {
if (!pflash_cfi02_register(0x30000000,
NULL,
"reptar.nand_flash",
pflash_size,
blk_by_legacy_dinfo(pflash),
sector_len,
pflash_size / sector_len,
1, 2, 0, 0, 0, 0, 0x555, 0x2AA, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}
}
else {
dmtd = drive_get(IF_MTD, 0, 0);
s->nand = nand_init(dmtd ? blk_by_legacy_dinfo(dmtd) : NULL, NAND_MFR_MICRON, 0xba);
nand_setpins(s->nand, 0, 0, 0, 1, 0); /* no write-protect */
omap_gpmc_attach_nand(s->cpu->gpmc, REPTAR_NAND_CS, s->nand);
}
/*
* (DRE) Define MMC if any
*/
dsd = drive_get(IF_SD, 0, 0);
if (dsd)
omap3_mmc_attach(s->cpu->omap3_mmc[0], blk_by_legacy_dinfo(dsd), 0, 0);
if (!pflash && !dmtd && !dsd)
hw_error("%s: SD or NAND image required", __FUNCTION__);
/* FAB revs >= 2516: 4030 interrupt is GPIO 0 (earlier ones were 112) */
s->twl4030 = twl4030_init(omap_i2c_bus(s->cpu->i2c[0]),
qdev_get_gpio_in(s->cpu->gpio, 0),
NULL,
NULL);
/* Wire up an I2C slave which returns EDID monitor information;
* newer Linux kernels won't turn on the display unless they
* detect a monitor over DDC.
*/
s->ddc = i2c_create_slave(omap_i2c_bus(s->cpu->i2c[2]), "i2c-ddc", 0x50);
omap_lcd_panel_attach(s->cpu->dss);
/* Strictly this should be a LAN9221 */
#if 0
if (nd_table[0].vlan) {
#endif /* 0 */
/* The ethernet chip hangs off the GPMC */
NICInfo *nd = &nd_table[0];
qemu_check_nic_model(nd, "lan9118");
s->eth = qdev_create(NULL, "lan9118");
qdev_set_nic_properties(s->eth, nd);
qdev_init_nofail(s->eth);
omap_gpmc_attach(s->cpu->gpmc, REPTAR_NET_CS,
sysbus_mmio_get_region(SYS_BUS_DEVICE(s->eth), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(s->eth), 0, qdev_get_gpio_in(s->cpu->gpio, 29));
#if 0
}
#endif /* 0 */
// Create reptar_sp6 with it's base address
s->sp6 = sysbus_create_simple("reptar_sp6",0x18000000,NULL);
// Connect reptar_sp6 to GPIO10 for the IRQ
sysbus_connect_irq(SYS_BUS_DEVICE(s->sp6), 0, qdev_get_gpio_in(s->cpu->gpio, 10));
}
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
{
BCM2835PeripheralState *s = BCM2835_PERIPHERALS(dev);
Object *obj;
MemoryRegion *ram;
Error *err = NULL;
uint64_t ram_size, vcram_size;
int n;
obj = object_property_get_link(OBJECT(dev), "ram", &err);
if (obj == NULL) {
error_setg(errp, "%s: required ram link not found: %s",
__func__, error_get_pretty(err));
return;
}
ram = MEMORY_REGION(obj);
ram_size = memory_region_size(ram);
/* Map peripherals and RAM into the GPU address space. */
memory_region_init_alias(&s->peri_mr_alias, OBJECT(s),
"bcm2835-peripherals", &s->peri_mr, 0,
memory_region_size(&s->peri_mr));
memory_region_add_subregion_overlap(&s->gpu_bus_mr, BCM2835_VC_PERI_BASE,
&s->peri_mr_alias, 1);
/* RAM is aliased four times (different cache configurations) on the GPU */
for (n = 0; n < 4; n++) {
memory_region_init_alias(&s->ram_alias[n], OBJECT(s),
"bcm2835-gpu-ram-alias[*]", ram, 0, ram_size);
memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n << 30,
&s->ram_alias[n], 0);
}
/* Interrupt Controller */
object_property_set_bool(OBJECT(&s->ic), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0));
sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));
/* UART0 */
qdev_prop_set_chr(DEVICE(s->uart0), "chardev", serial_hds[0]);
object_property_set_bool(OBJECT(s->uart0), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, UART0_OFFSET,
sysbus_mmio_get_region(s->uart0, 0));
sysbus_connect_irq(s->uart0, 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_UART));
/* AUX / UART1 */
qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hds[1]);
object_property_set_bool(OBJECT(&s->aux), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, UART1_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_AUX));
/* Mailboxes */
object_property_set_bool(OBJECT(&s->mboxes), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, ARMCTRL_0_SBM_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mboxes), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mboxes), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ,
INTERRUPT_ARM_MAILBOX));
/* Framebuffer */
vcram_size = object_property_get_uint(OBJECT(s), "vcram-size", &err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_uint(OBJECT(&s->fb), ram_size - vcram_size,
"vcram-base", &err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->fb), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_FB << MBOX_AS_CHAN_SHIFT,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->fb), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fb), 0,
qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB));
/* Property channel */
object_property_set_bool(OBJECT(&s->property), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->mbox_mr,
MBOX_CHAN_PROPERTY << MBOX_AS_CHAN_SHIFT,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->property), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->property), 0,
qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY));
/* Random Number Generator */
object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, RNG_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0));
/* Extended Mass Media Controller */
object_property_set_int(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg",
&err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->sdhci), true, "pending-insert-quirk",
&err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, EMMC_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_ARASANSDIO));
/* SDHOST */
object_property_set_bool(OBJECT(&s->sdhost), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_SDIO));
/* DMA Channels */
object_property_set_bool(OBJECT(&s->dma), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, DMA_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 0));
memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1));
for (n = 0; n <= 12; n++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), n,
qdev_get_gpio_in_named(DEVICE(&s->ic),
BCM2835_IC_GPU_IRQ,
INTERRUPT_DMA0 + n));
}
/* GPIO */
object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, GPIO_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus",
&err);
if (err) {
error_propagate(errp, err);
return;
}
}
static void a15mp_priv_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
A15MPPrivState *s = A15MPCORE_PRIV(dev);
DeviceState *gicdev;
SysBusDevice *busdev;
int i;
Error *err = NULL;
gicdev = DEVICE(&s->gic);
qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
busdev = SYS_BUS_DEVICE(&s->gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(sbd, busdev);
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
/* Wire the outputs from each CPU's generic timer to the
* appropriate GIC PPI inputs
*/
for (i = 0; i < s->num_cpu; i++) {
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
int ppibase = s->num_irq - 32 + i * 32;
/* physical timer; we wire it up to the non-secure timer's ID,
* since a real A15 always has TrustZone but QEMU doesn't.
*/
qdev_connect_gpio_out(cpudev, 0,
qdev_get_gpio_in(gicdev, ppibase + 30));
/* virtual timer */
qdev_connect_gpio_out(cpudev, 1,
qdev_get_gpio_in(gicdev, ppibase + 27));
qdev_connect_gpio_out(cpudev, 2,
qdev_get_gpio_in(gicdev, ppibase + 26));
if (!kvm_enabled()) {
/* Maintenance interrupt. */
sysbus_connect_irq(busdev, s->num_cpu * 2 + i,
qdev_get_gpio_in(gicdev, ppibase + 25));
}
}
/* Memory map (addresses are offsets from PERIPHBASE):
* 0x0000-0x0fff -- reserved
* 0x1000-0x1fff -- GIC Distributor
* 0x2000-0x2fff -- GIC CPU interface
* 0x4000-0x4fff -- GIC virtual interface control (only with emulation)
* 0x5000-0x5fff -- GIC virtual interface control alias (only with emul)
* 0x6000-0x7fff -- GIC virtual CPU interface (only with emulation)
*/
memory_region_add_subregion(&s->container, 0x1000,
sysbus_mmio_get_region(busdev, 0));
memory_region_add_subregion(&s->container, 0x2000,
sysbus_mmio_get_region(busdev, 1));
if (!kvm_enabled()) {
int hregion = (s->num_cpu + 1) + 1;
int vregion = (s->num_cpu + 1) * 2 + 1;
/* Add the Hypervisor (virtual interface control) reg areas. */
memory_region_add_subregion(&s->container, 0x4000,
sysbus_mmio_get_region(busdev, hregion));
for (i = 1; i <= s->num_cpu; i++) {
memory_region_add_subregion(&s->container, 0x5000 + i * 0x200,
sysbus_mmio_get_region(busdev,
hregion + i));
}
memory_region_add_subregion(&s->container, 0x6000,
sysbus_mmio_get_region(busdev, vregion));
}
}
void ppce500_init(QEMUMachineInitArgs *args, PPCE500Params *params)
{
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
PCIBus *pci_bus;
CPUPPCState *env = NULL;
uint64_t elf_entry;
uint64_t elf_lowaddr;
hwaddr entry=0;
hwaddr loadaddr=UIMAGE_LOAD_BASE;
target_long kernel_size=0;
target_ulong dt_base = 0;
target_ulong initrd_base = 0;
target_long initrd_size = 0;
target_ulong cur_base = 0;
int i;
unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
qemu_irq **irqs, *mpic;
DeviceState *dev;
CPUPPCState *firstenv = NULL;
MemoryRegion *ccsr_addr_space;
SysBusDevice *s;
PPCE500CCSRState *ccsr;
/* Setup CPUs */
if (args->cpu_model == NULL) {
args->cpu_model = "e500v2_v30";
}
irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
for (i = 0; i < smp_cpus; i++) {
PowerPCCPU *cpu;
CPUState *cs;
qemu_irq *input;
cpu = cpu_ppc_init(args->cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to initialize CPU!\n");
exit(1);
}
env = &cpu->env;
cs = CPU(cpu);
if (!firstenv) {
firstenv = env;
}
irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
input = (qemu_irq *)env->irq_inputs;
irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i;
env->mpic_iack = MPC8544_CCSRBAR_BASE +
MPC8544_MPIC_REGS_OFFSET + 0xa0;
ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
/* Register reset handler */
if (!i) {
/* Primary CPU */
struct boot_info *boot_info;
boot_info = g_malloc0(sizeof(struct boot_info));
qemu_register_reset(ppce500_cpu_reset, cpu);
env->load_info = boot_info;
} else {
/* Secondary CPUs */
qemu_register_reset(ppce500_cpu_reset_sec, cpu);
}
}
env = firstenv;
/* Fixup Memory size on a alignment boundary */
ram_size &= ~(RAM_SIZES_ALIGN - 1);
args->ram_size = ram_size;
/* Register Memory */
memory_region_init_ram(ram, NULL, "mpc8544ds.ram", ram_size);
vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space_mem, 0, ram);
dev = qdev_create(NULL, "e500-ccsr");
object_property_add_child(qdev_get_machine(), "e500-ccsr",
OBJECT(dev), NULL);
qdev_init_nofail(dev);
ccsr = CCSR(dev);
ccsr_addr_space = &ccsr->ccsr_space;
memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
ccsr_addr_space);
mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs);
/* Serial */
if (serial_hds[0]) {
serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
0, mpic[42], 399193,
serial_hds[0], DEVICE_BIG_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
0, mpic[42], 399193,
serial_hds[1], DEVICE_BIG_ENDIAN);
}
/* General Utility device */
dev = qdev_create(NULL, "mpc8544-guts");
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
sysbus_mmio_get_region(s, 0));
/* PCI */
dev = qdev_create(NULL, "e500-pcihost");
qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]);
sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]);
sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]);
memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
sysbus_mmio_get_region(s, 0));
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
if (!pci_bus)
printf("couldn't create PCI controller!\n");
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO);
if (pci_bus) {
/* Register network interfaces. */
for (i = 0; i < nb_nics; i++) {
pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL);
}
}
/* Register spinning region */
sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
/* Load kernel. */
if (args->kernel_filename) {
kernel_size = load_uimage(args->kernel_filename, &entry,
&loadaddr, NULL);
if (kernel_size < 0) {
kernel_size = load_elf(args->kernel_filename, NULL, NULL,
&elf_entry, &elf_lowaddr, NULL, 1,
ELF_MACHINE, 0);
entry = elf_entry;
loadaddr = elf_lowaddr;
}
/* XXX try again as binary */
if (kernel_size < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
args->kernel_filename);
exit(1);
}
cur_base = loadaddr + kernel_size;
/* Reserve space for dtb */
dt_base = (cur_base + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
cur_base += DTB_MAX_SIZE;
}
/* Load initrd. */
if (args->initrd_filename) {
initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
initrd_size = load_image_targphys(args->initrd_filename, initrd_base,
ram_size - initrd_base);
if (initrd_size < 0) {
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
args->initrd_filename);
exit(1);
}
cur_base = initrd_base + initrd_size;
}
/* If we're loading a kernel directly, we must load the device tree too. */
if (args->kernel_filename) {
struct boot_info *boot_info;
int dt_size;
dt_size = ppce500_prep_device_tree(args, params, dt_base,
initrd_base, initrd_size);
if (dt_size < 0) {
fprintf(stderr, "couldn't load device tree\n");
exit(1);
}
assert(dt_size < DTB_MAX_SIZE);
boot_info = env->load_info;
boot_info->entry = entry;
boot_info->dt_base = dt_base;
boot_info->dt_size = dt_size;
}
if (kvm_enabled()) {
kvmppc_init();
}
}
static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model)
{
MemoryRegion *address_space = get_system_memory();
char *filename;
int bios_size, n;
MIPSCPU *cpu;
CPUClass *cc;
CPUMIPSState *env;
qemu_irq *i8259;
rc4030_dma *dmas;
IOMMUMemoryRegion *rc4030_dma_mr;
MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
MemoryRegion *isa_io = g_new(MemoryRegion, 1);
MemoryRegion *rtc = g_new(MemoryRegion, 1);
MemoryRegion *i8042 = g_new(MemoryRegion, 1);
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev, *rc4030;
SysBusDevice *sysbus;
ISABus *isa_bus;
ISADevice *pit;
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset, dma_enable;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *bios2 = g_new(MemoryRegion, 1);
/* init CPUs */
cpu = MIPS_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
/* Chipset returns 0 in invalid reads and do not raise data exceptions.
* However, we can't simply add a global memory region to catch
* everything, as memory core directly call unassigned_mem_read/write
* on some invalid accesses, which call do_unassigned_access on the
* CPU, which raise an exception.
* Handle that case by hijacking the do_unassigned_access method on
* the CPU, and do not raise exceptions for data access. */
cc = CPU_GET_CLASS(cpu);
real_do_unassigned_access = cc->do_unassigned_access;
cc->do_unassigned_access = mips_jazz_do_unassigned_access;
/* allocate RAM */
memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
machine->ram_size);
memory_region_add_subregion(address_space, 0, ram);
memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
&error_fatal);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
0, MAGNUM_BIOS_SIZE);
memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
/* load the BIOS image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_targphys(filename, 0xfff00000LL,
MAGNUM_BIOS_SIZE);
g_free(filename);
} else {
bios_size = -1;
}
if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
error_report("Could not load MIPS bios '%s'", bios_name);
exit(1);
}
/* Init CPU internal devices */
cpu_mips_irq_init_cpu(cpu);
cpu_mips_clock_init(cpu);
/* Chipset */
rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
sysbus = SYS_BUS_DEVICE(rc4030);
sysbus_connect_irq(sysbus, 0, env->irq[6]);
sysbus_connect_irq(sysbus, 1, env->irq[3]);
memory_region_add_subregion(address_space, 0x80000000,
sysbus_mmio_get_region(sysbus, 0));
memory_region_add_subregion(address_space, 0xf0000000,
sysbus_mmio_get_region(sysbus, 1));
memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
/* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
memory_region_add_subregion(address_space, 0x90000000, isa_io);
memory_region_add_subregion(address_space, 0x91000000, isa_mem);
isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
/* ISA devices */
i8259 = i8259_init(isa_bus, env->irq[4]);
isa_bus_irqs(isa_bus, i8259);
DMA_init(isa_bus, 0);
pit = pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_bus, pit);
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
dev = qdev_create(NULL, "sysbus-g364");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x60080000);
sysbus_mmio_map(sysbus, 1, 0x40000000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
{
/* Simple ROM, so user doesn't have to provide one */
MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
&error_fatal);
memory_region_set_readonly(rom_mr, true);
uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
memory_region_add_subregion(address_space, 0x60000000, rom_mr);
rom[0] = 0x10; /* Mips G364 */
}
break;
case JAZZ_PICA61:
isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
break;
default:
break;
}
/* Network controller */
for (n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
if (!nd->model)
nd->model = g_strdup("dp83932");
if (strcmp(nd->model, "dp83932") == 0) {
qemu_check_nic_model(nd, "dp83932");
dev = qdev_create(NULL, "dp8393x");
qdev_set_nic_properties(dev, nd);
qdev_prop_set_uint8(dev, "it_shift", 2);
qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80001000);
sysbus_mmio_map(sysbus, 1, 0x8000b000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
break;
} else if (is_help_option(nd->model)) {
fprintf(stderr, "qemu: Supported NICs: dp83932\n");
exit(1);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
exit(1);
}
}
/* SCSI adapter */
esp_init(0x80002000, 0,
rc4030_dma_read, rc4030_dma_write, dmas[0],
qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
/* Floppy */
for (n = 0; n < MAX_FD; n++) {
fds[n] = drive_get(IF_FLOPPY, 0, n);
}
/* FIXME: we should enable DMA with a custom IsaDma device */
fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
/* Real time clock */
rtc_init(isa_bus, 1980, NULL);
memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
i8042, 0x1000, 0x1);
memory_region_add_subregion(address_space, 0x80005000, i8042);
/* Serial ports */
if (serial_hds[0]) {
serial_mm_init(address_space, 0x80006000, 0,
qdev_get_gpio_in(rc4030, 8), 8000000/16,
serial_hds[0], DEVICE_NATIVE_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(address_space, 0x80007000, 0,
qdev_get_gpio_in(rc4030, 9), 8000000/16,
serial_hds[1], DEVICE_NATIVE_ENDIAN);
}
/* Parallel port */
if (parallel_hds[0])
parallel_mm_init(address_space, 0x80008000, 0,
qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
/* NVRAM */
dev = qdev_create(NULL, "ds1225y");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80009000);
/* LED indicator */
sysbus_create_simple("jazz-led", 0x8000f000, NULL);
}
static void a15mp_priv_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
A15MPPrivState *s = A15MPCORE_PRIV(dev);
DeviceState *gicdev;
SysBusDevice *busdev;
int i;
Error *err = NULL;
bool has_el3;
bool has_el2 = false;
Object *cpuobj;
gicdev = DEVICE(&s->gic);
qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
if (!kvm_irqchip_in_kernel()) {
/* Make the GIC's TZ support match the CPUs. We assume that
* either all the CPUs have TZ, or none do.
*/
cpuobj = OBJECT(qemu_get_cpu(0));
has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
object_property_get_bool(cpuobj, "has_el3", &error_abort);
qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
/* Similarly for virtualization support */
has_el2 = object_property_find(cpuobj, "has_el2", NULL) &&
object_property_get_bool(cpuobj, "has_el2", &error_abort);
qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2);
}
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
busdev = SYS_BUS_DEVICE(&s->gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(sbd, busdev);
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
/* Wire the outputs from each CPU's generic timer to the
* appropriate GIC PPI inputs
*/
for (i = 0; i < s->num_cpu; i++) {
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
int ppibase = s->num_irq - 32 + i * 32;
int irq;
/* Mapping from the output timer irq lines from the CPU to the
* GIC PPI inputs used on the A15:
*/
const int timer_irq[] = {
[GTIMER_PHYS] = 30,
[GTIMER_VIRT] = 27,
[GTIMER_HYP] = 26,
[GTIMER_SEC] = 29,
};
for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
qdev_connect_gpio_out(cpudev, irq,
qdev_get_gpio_in(gicdev,
ppibase + timer_irq[irq]));
}
if (has_el2) {
/* Connect the GIC maintenance interrupt to PPI ID 25 */
sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu,
qdev_get_gpio_in(gicdev, ppibase + 25));
}
}
/* Memory map (addresses are offsets from PERIPHBASE):
* 0x0000-0x0fff -- reserved
* 0x1000-0x1fff -- GIC Distributor
* 0x2000-0x3fff -- GIC CPU interface
* 0x4000-0x4fff -- GIC virtual interface control for this CPU
* 0x5000-0x51ff -- GIC virtual interface control for CPU 0
* 0x5200-0x53ff -- GIC virtual interface control for CPU 1
* 0x5400-0x55ff -- GIC virtual interface control for CPU 2
* 0x5600-0x57ff -- GIC virtual interface control for CPU 3
* 0x6000-0x7fff -- GIC virtual CPU interface
*/
memory_region_add_subregion(&s->container, 0x1000,
sysbus_mmio_get_region(busdev, 0));
memory_region_add_subregion(&s->container, 0x2000,
sysbus_mmio_get_region(busdev, 1));
if (has_el2) {
memory_region_add_subregion(&s->container, 0x4000,
sysbus_mmio_get_region(busdev, 2));
memory_region_add_subregion(&s->container, 0x6000,
sysbus_mmio_get_region(busdev, 3));
for (i = 0; i < s->num_cpu; i++) {
hwaddr base = 0x5000 + i * 0x200;
MemoryRegion *mr = sysbus_mmio_get_region(busdev,
4 + s->num_cpu + i);
memory_region_add_subregion(&s->container, base, mr);
}
}
}
static void vexpress_common_init(MachineState *machine)
{
VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
VEDBoardInfo *daughterboard = vmc->daughterboard;
DeviceState *dev, *sysctl, *pl041;
qemu_irq pic[64];
uint32_t sys_id;
DriveInfo *dinfo;
pflash_t *pflash0;
ram_addr_t vram_size, sram_size;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *vram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *flashalias = g_new(MemoryRegion, 1);
MemoryRegion *flash0mem;
const hwaddr *map = daughterboard->motherboard_map;
int i;
daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic);
/*
* If a bios file was provided, attempt to map it into memory
*/
if (bios_name) {
char *fn;
int image_size;
if (drive_get(IF_PFLASH, 0, 0)) {
error_report("The contents of the first flash device may be "
"specified with -bios or with -drive if=pflash... "
"but you cannot use both options at once");
exit(1);
}
fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (!fn) {
error_report("Could not find ROM image '%s'", bios_name);
exit(1);
}
image_size = load_image_targphys(fn, map[VE_NORFLASH0],
VEXPRESS_FLASH_SIZE);
g_free(fn);
if (image_size < 0) {
error_report("Could not load ROM image '%s'", bios_name);
exit(1);
}
}
/* Motherboard peripherals: the wiring is the same but the
* addresses vary between the legacy and A-Series memory maps.
*/
sys_id = 0x1190f500;
sysctl = qdev_create(NULL, "realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
qdev_prop_set_uint32(sysctl, "len-db-voltage",
daughterboard->num_voltage_sensors);
for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
char *propname = g_strdup_printf("db-voltage[%d]", i);
qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
g_free(propname);
}
qdev_prop_set_uint32(sysctl, "len-db-clock",
daughterboard->num_clocks);
for (i = 0; i < daughterboard->num_clocks; i++) {
char *propname = g_strdup_printf("db-clock[%d]", i);
qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
g_free(propname);
}
qdev_init_nofail(sysctl);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
/* VE_SP810: not modelled */
/* VE_SERIALPCI: not modelled */
pl041 = qdev_create(NULL, "pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
qdev_init_nofail(pl041);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
/* Wire up MMC card detect and read-only signals */
qdev_connect_gpio_out(dev, 0,
qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
qdev_connect_gpio_out(dev, 1,
qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
sysbus_create_simple("pl011", map[VE_UART0], pic[5]);
sysbus_create_simple("pl011", map[VE_UART1], pic[6]);
sysbus_create_simple("pl011", map[VE_UART2], pic[7]);
sysbus_create_simple("pl011", map[VE_UART3], pic[8]);
sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
/* VE_SERIALDVI: not modelled */
sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
/* VE_COMPACTFLASH: not modelled */
sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
dinfo = drive_get_next(IF_PFLASH);
pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
dinfo);
if (!pflash0) {
fprintf(stderr, "vexpress: error registering flash 0.\n");
exit(1);
}
if (map[VE_NORFLASHALIAS] != -1) {
/* Map flash 0 as an alias into low memory */
flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
flash0mem, 0, VEXPRESS_FLASH_SIZE);
memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
}
dinfo = drive_get_next(IF_PFLASH);
if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
dinfo)) {
fprintf(stderr, "vexpress: error registering flash 1.\n");
exit(1);
}
sram_size = 0x2000000;
memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
&error_abort);
vmstate_register_ram_global(sram);
memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
vram_size = 0x800000;
memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
&error_abort);
vmstate_register_ram_global(vram);
memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
/* 0x4e000000 LAN9118 Ethernet */
if (nd_table[0].used) {
lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
}
/* VE_USB: not modelled */
/* VE_DAPROM: not modelled */
/* Create mmio transports, so the user can create virtio backends
* (which will be automatically plugged in to the transports). If
* no backend is created the transport will just sit harmlessly idle.
*/
for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
pic[40 + i]);
}
daughterboard->bootinfo.ram_size = machine->ram_size;
daughterboard->bootinfo.kernel_filename = machine->kernel_filename;
daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline;
daughterboard->bootinfo.initrd_filename = machine->initrd_filename;
daughterboard->bootinfo.nb_cpus = smp_cpus;
daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
daughterboard->bootinfo.loader_start = daughterboard->loader_start;
daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
/* Indicate that when booting Linux we should be in secure state */
daughterboard->bootinfo.secure_boot = true;
arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
}
static void sun4uv_init(MemoryRegion *address_space_mem,
MachineState *machine,
const struct hwdef *hwdef)
{
SPARCCPU *cpu;
Nvram *nvram;
unsigned int i;
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
ISABus *isa_bus;
SysBusDevice *s;
qemu_irq *ivec_irqs, *pbm_irqs;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DriveInfo *fd[MAX_FD];
FWCfgState *fw_cfg;
/* init CPUs */
cpu = cpu_devinit(machine->cpu_model, hwdef);
/* set up devices */
ram_init(0, machine->ram_size);
prom_init(hwdef->prom_addr, bios_name);
ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX);
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
&pci_bus3, &pbm_irqs);
pci_vga_init(pci_bus);
// XXX Should be pci_bus3
isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
i = 0;
if (hwdef->console_serial_base) {
serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
i++;
}
serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS);
parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
for(i = 0; i < nb_nics; i++)
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
ide_drive_get(hd, ARRAY_SIZE(hd));
pci_cmd646_ide_init(pci_bus, hd, 1);
isa_create_simple(isa_bus, "i8042");
for(i = 0; i < MAX_FD; i++) {
fd[i] = drive_get(IF_FLOPPY, 0, i);
}
fdctrl_init_isa(isa_bus, fd);
/* Map NVRAM into I/O (ebus) space */
nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
s = SYS_BUS_DEVICE(nvram);
memory_region_add_subregion(get_system_io(), 0x2000,
sysbus_mmio_get_region(s, 0));
initrd_size = 0;
initrd_addr = 0;
kernel_size = sun4u_load_kernel(machine->kernel_filename,
machine->initrd_filename,
ram_size, &initrd_size, &initrd_addr,
&kernel_addr, &kernel_entry);
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
machine->boot_order,
kernel_addr, kernel_size,
machine->kernel_cmdline,
initrd_addr, initrd_size,
/* XXX: need an option to load a NVRAM image */
0,
graphic_width, graphic_height, graphic_depth,
(uint8_t *)&nd_table[0].macaddr);
fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (machine->kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
strlen(machine->kernel_cmdline) + 1);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
}
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
static void vexpress_common_init(VEDBoardInfo *daughterboard,
QEMUMachineInitArgs *args)
{
DeviceState *dev, *sysctl, *pl041;
qemu_irq pic[64];
uint32_t sys_id;
DriveInfo *dinfo;
pflash_t *pflash0;
ram_addr_t vram_size, sram_size;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *vram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *flashalias = g_new(MemoryRegion, 1);
MemoryRegion *flash0mem;
const hwaddr *map = daughterboard->motherboard_map;
int i;
daughterboard->init(daughterboard, args->ram_size, args->cpu_model, pic);
/* Motherboard peripherals: the wiring is the same but the
* addresses vary between the legacy and A-Series memory maps.
*/
sys_id = 0x1190f500;
sysctl = qdev_create(NULL, "realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
qdev_prop_set_uint32(sysctl, "len-db-voltage",
daughterboard->num_voltage_sensors);
for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
char *propname = g_strdup_printf("db-voltage[%d]", i);
qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
g_free(propname);
}
qdev_prop_set_uint32(sysctl, "len-db-clock",
daughterboard->num_clocks);
for (i = 0; i < daughterboard->num_clocks; i++) {
char *propname = g_strdup_printf("db-clock[%d]", i);
qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
g_free(propname);
}
qdev_init_nofail(sysctl);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
/* VE_SP810: not modelled */
/* VE_SERIALPCI: not modelled */
pl041 = qdev_create(NULL, "pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
qdev_init_nofail(pl041);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
/* Wire up MMC card detect and read-only signals */
qdev_connect_gpio_out(dev, 0,
qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
qdev_connect_gpio_out(dev, 1,
qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
sysbus_create_simple("pl011", map[VE_UART0], pic[5]);
sysbus_create_simple("pl011", map[VE_UART1], pic[6]);
sysbus_create_simple("pl011", map[VE_UART2], pic[7]);
sysbus_create_simple("pl011", map[VE_UART3], pic[8]);
sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
/* VE_SERIALDVI: not modelled */
sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
/* VE_COMPACTFLASH: not modelled */
sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
dinfo = drive_get_next(IF_PFLASH);
pflash0 = pflash_cfi01_register(map[VE_NORFLASH0], NULL, "vexpress.flash0",
VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
VEXPRESS_FLASH_SECT_SIZE,
VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
0x00, 0x89, 0x00, 0x18, 0);
if (!pflash0) {
fprintf(stderr, "vexpress: error registering flash 0.\n");
exit(1);
}
if (map[VE_NORFLASHALIAS] != -1) {
/* Map flash 0 as an alias into low memory */
flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
flash0mem, 0, VEXPRESS_FLASH_SIZE);
memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
}
dinfo = drive_get_next(IF_PFLASH);
if (!pflash_cfi01_register(map[VE_NORFLASH1], NULL, "vexpress.flash1",
VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
VEXPRESS_FLASH_SECT_SIZE,
VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
0x00, 0x89, 0x00, 0x18, 0)) {
fprintf(stderr, "vexpress: error registering flash 1.\n");
exit(1);
}
sram_size = 0x2000000;
memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size);
vmstate_register_ram_global(sram);
memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
vram_size = 0x800000;
memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size);
vmstate_register_ram_global(vram);
memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
/* 0x4e000000 LAN9118 Ethernet */
if (nd_table[0].used) {
lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
}
/* VE_USB: not modelled */
/* VE_DAPROM: not modelled */
/* Create mmio transports, so the user can create virtio backends
* (which will be automatically plugged in to the transports). If
* no backend is created the transport will just sit harmlessly idle.
*/
for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
pic[40 + i]);
}
daughterboard->bootinfo.ram_size = args->ram_size;
daughterboard->bootinfo.kernel_filename = args->kernel_filename;
daughterboard->bootinfo.kernel_cmdline = args->kernel_cmdline;
daughterboard->bootinfo.initrd_filename = args->initrd_filename;
daughterboard->bootinfo.nb_cpus = smp_cpus;
daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
daughterboard->bootinfo.loader_start = daughterboard->loader_start;
daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
}
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
{
BCM2835PeripheralState *s = BCM2835_PERIPHERALS(dev);
Object *obj;
MemoryRegion *ram;
Error *err = NULL;
uint64_t ram_size, vcram_size;
int n;
obj = object_property_get_link(OBJECT(dev), "ram", &err);
if (obj == NULL) {
error_setg(errp, "%s: required ram link not found: %s",
__func__, error_get_pretty(err));
return;
}
ram = MEMORY_REGION(obj);
ram_size = memory_region_size(ram);
/* Map peripherals and RAM into the GPU address space. */
memory_region_init_alias(&s->peri_mr_alias, OBJECT(s),
"bcm2835-peripherals", &s->peri_mr, 0,
memory_region_size(&s->peri_mr));
memory_region_add_subregion_overlap(&s->gpu_bus_mr, BCM2835_VC_PERI_BASE,
&s->peri_mr_alias, 1);
/* RAM is aliased four times (different cache configurations) on the GPU */
for (n = 0; n < 4; n++) {
memory_region_init_alias(&s->ram_alias[n], OBJECT(s),
"bcm2835-gpu-ram-alias[*]", ram, 0, ram_size);
memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n << 30,
&s->ram_alias[n], 0);
}
/* Interrupt Controller */
object_property_set_bool(OBJECT(&s->ic), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0));
sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));
/* UART0 */
qdev_prop_set_chr(DEVICE(s->uart0), "chardev", serial_hd(0));
object_property_set_bool(OBJECT(s->uart0), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, UART0_OFFSET,
sysbus_mmio_get_region(s->uart0, 0));
sysbus_connect_irq(s->uart0, 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_UART));
/* AUX / UART1 */
qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hd(1));
object_property_set_bool(OBJECT(&s->aux), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, UART1_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_AUX));
/* System timer */
object_property_set_bool(OBJECT(&s->st), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, ST_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->st), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->st), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_TIMER0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->st), 1,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_TIMER1));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->st), 2,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_TIMER2));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->st), 3,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_TIMER3));
/* ARM timer */
object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, ARMCTRL_TIMER0_1_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ,
INTERRUPT_ARM_TIMER));
/* USB controller */
object_property_set_bool(OBJECT(&s->usb), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, USB_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->usb), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_USB));
/* MPHI - Message-based Parallel Host Interface */
object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_HOSTPORT));
/* Mailboxes */
object_property_set_bool(OBJECT(&s->mboxes), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, ARMCTRL_0_SBM_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mboxes), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mboxes), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ,
INTERRUPT_ARM_MAILBOX));
/* Power management */
object_property_set_bool(OBJECT(&s->power), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_POWER << MBOX_AS_CHAN_SHIFT,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->power), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->power), 0,
qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_POWER));
/* Framebuffer */
vcram_size = object_property_get_uint(OBJECT(s), "vcram-size", &err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_uint(OBJECT(&s->fb), ram_size - vcram_size,
"vcram-base", &err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->fb), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_FB << MBOX_AS_CHAN_SHIFT,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->fb), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fb), 0,
qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB));
/* Property channel */
object_property_set_bool(OBJECT(&s->property), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->mbox_mr,
MBOX_CHAN_PROPERTY << MBOX_AS_CHAN_SHIFT,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->property), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->property), 0,
qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY));
/* Random Number Generator */
object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, RNG_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0));
/* Extended Mass Media Controller
*
* Compatible with:
* - SD Host Controller Specification Version 3.0 Draft 1.0
* - SDIO Specification Version 3.0
* - MMC Specification Version 4.4
*
* For the exact details please refer to the Arasan documentation:
* SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf
*/
object_property_set_uint(OBJECT(&s->sdhci), 3, "sd-spec-version", &err);
object_property_set_uint(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg",
&err);
object_property_set_bool(OBJECT(&s->sdhci), true, "pending-insert-quirk",
&err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, EMMC_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_ARASANSDIO));
/* SDHOST */
object_property_set_bool(OBJECT(&s->sdhost), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_SDIO));
/* DMA Channels */
object_property_set_bool(OBJECT(&s->dma), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, DMA_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 0));
memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1));
for (n = 0; n <= 12; n++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), n,
qdev_get_gpio_in_named(DEVICE(&s->ic),
BCM2835_IC_GPU_IRQ,
INTERRUPT_DMA0 + n));
}
/* GPIO */
object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, GPIO_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus",
&err);
if (err) {
error_propagate(errp, err);
return;
}
}
