/**
****************************************************************************************
* @brief GPIO functionn configuration.
*
* Set Pins as gpio pin or function pin
*****************************************************************************************
*/
static void SystemIOCfg(void)
{
// pin mux
syscon_SetPMCR0(QN_SYSCON, P00_UART0_TXD_PIN_CTRL
| P01_GPIO_1_PIN_CTRL
| P02_GPIO_2_PIN_CTRL
| P03_GPIO_3_PIN_CTRL
| P04_GPIO_4_PIN_CTRL
| P05_GPIO_5_PIN_CTRL
| P06_SW_DAT_PIN_CTRL
| P07_SW_CLK_PIN_CTRL
| P10_GPIO_8_PIN_CTRL
| P11_GPIO_9_PIN_CTRL
| P12_GPIO_10_PIN_CTRL
| P13_GPIO_11_PIN_CTRL
| P14_GPIO_12_PIN_CTRL
| P15_GPIO_13_PIN_CTRL
| P16_GPIO_14_PIN_CTRL
| P17_UART0_RXD_PIN_CTRL
);
syscon_SetPMCR1(QN_SYSCON, P20_UART1_RXD_PIN_CTRL
| P21_UART1_TXD_PIN_CTRL
| P22_GPIO_18_PIN_CTRL
| P23_GPIO_19_PIN_CTRL
| P24_GPIO_20_PIN_CTRL
| P25_GPIO_21_PIN_CTRL
| P26_GPIO_22_PIN_CTRL
| P27_GPIO_23_PIN_CTRL
| P30_GPIO_24_PIN_CTRL
| P31_GPIO_25_PIN_CTRL
| P32_GPIO_26_PIN_CTRL
| P33_GPIO_27_PIN_CTRL
| P34_GPIO_28_PIN_CTRL
| P35_GPIO_29_PIN_CTRL
| P36_GPIO_30_PIN_CTRL
);
/**
* Pin select
**** USART1
* Pin37 <--> USART1_CTS
* Pin20 <--> USART1_RXD
**** SPI0
* Pin32 <--> SPI0_DIN
* Pin33 <--> SPI0_DAT
* Pin34 <--> SPI0_CLK
* Pin35 <--> SPI0_CS0
*/
syscon_SetPMCR2(QN_SYSCON, SYSCON_MASK_UART1_PIN_SEL | SYSCON_MASK_SPI0_PIN_SEL);
// driver ability
syscon_SetPDCR(QN_SYSCON, 0x0); // 0 : low driver, 1 : high driver
// pin pull ( 00 : High-Z, 01 : Pull-down, 10 : Pull-up, 11 : Reserved )
syscon_SetPPCR0(QN_SYSCON, 0xAAAA5AAA);
syscon_SetPPCR1(QN_SYSCON, 0x2AAAAAAA);
}
/**
****************************************************************************************
* @brief GPIO functionn configuration.
*
* Set Pins as gpio pin or function pin
*****************************************************************************************
*/
static void SystemIOCfg(void)
{
// pin mux
syscon_SetPMCR0(QN_SYSCON, P00_UART0_TXD_PIN_CTRL
| P01_GPIO_1_PIN_CTRL
| P02_GPIO_2_PIN_CTRL
| P03_GPIO_3_PIN_CTRL
| P04_GPIO_4_PIN_CTRL
| P05_GPIO_5_PIN_CTRL
| P06_SW_DAT_PIN_CTRL
| P07_SW_CLK_PIN_CTRL
| P10_GPIO_8_PIN_CTRL
| P11_GPIO_9_PIN_CTRL
| P12_GPIO_10_PIN_CTRL
| P13_GPIO_11_PIN_CTRL
| P14_GPIO_12_PIN_CTRL
| P15_GPIO_13_PIN_CTRL
| P16_GPIO_14_PIN_CTRL
| P17_UART0_RXD_PIN_CTRL
);
syscon_SetPMCR1(QN_SYSCON, P20_GPIO_16_PIN_CTRL
| P21_GPIO_17_PIN_CTRL
| P22_GPIO_18_PIN_CTRL
| P23_GPIO_19_PIN_CTRL
| P24_GPIO_20_PIN_CTRL
| P25_GPIO_21_PIN_CTRL
| P26_PWM1_PIN_CTRL
| P27_GPIO_23_PIN_CTRL
| P30_GPIO_24_PIN_CTRL
| P31_GPIO_25_PIN_CTRL
#if (defined(CFG_HCI_SPI))
| P32_SPI0_DIN_PIN_CTRL //P3.2 spi1 data in
| P33_SPI0_DAT_PIN_CTRL //P3.3 spi1 data out
| P34_SPI0_CLK_PIN_CTRL //P3.4 spi1 clk
| P35_SPI0_CS0_PIN_CTRL //P3.5 spi1 cs
#else
| P32_GPIO_26_PIN_CTRL
| P33_GPIO_27_PIN_CTRL
| P34_GPIO_28_PIN_CTRL
| P35_GPIO_29_PIN_CTRL
#endif
| P36_GPIO_30_PIN_CTRL
);
// pin select
syscon_SetPMCR2(QN_SYSCON, SYSCON_MASK_UART1_PIN_SEL | SYSCON_MASK_SPI0_PIN_SEL);
// driver ability
syscon_SetPDCR(QN_SYSCON, 0x0); // 0 : low driver, 1 : high driver
// pin pull ( 00 : High-Z, 01 : Pull-down, 10 : Pull-up, 11 : Reserved )
syscon_SetPPCR0(QN_SYSCON, 0xAAAA5AAA);
syscon_SetPPCR1(QN_SYSCON, 0x2AAAAAAA);
}
void pwm_io_config(void)
{
uint32_t reg;
uint32_t reg_mask;
/**
* PMCR0 register pin configure
*/
reg = P07_SW_CLK_PIN_CTRL | P06_SW_DAT_PIN_CTRL;
reg_mask = P07_MASK_PIN_CTRL | P06_MASK_PIN_CTRL;
syscon_SetPMCR0WithMask(QN_SYSCON, reg_mask, reg);
/**
* PMCR1 register pin configure
*/
reg = P27_PWM0_PIN_CTRL | P26_PWM1_PIN_CTRL;
reg_mask = P27_MASK_PIN_CTRL | P26_MASK_PIN_CTRL;
syscon_SetPMCR1WithMask(QN_SYSCON, reg_mask, reg);
// pin pull ( 00 : High-Z, 01 : Pull-down, 10 : Pull-up, 11 : Reserved )
syscon_SetPPCR0(QN_SYSCON, 0xAAAA5AAA);
syscon_SetPPCR1(QN_SYSCON, 0x2AAAAAAA);
}
/**
****************************************************************************************
* @brief GPIO functionn configuration.
*
* Set Pins as gpio pin or function pin
*****************************************************************************************
*/
static void SystemIOCfg(void)
{
// pin mux
syscon_SetPMCR0(QN_SYSCON, P00_UART0_TXD_PIN_CTRL
| P01_GPIO_1_PIN_CTRL
| P02_GPIO_2_PIN_CTRL
| P03_GPIO_3_PIN_CTRL
| P04_GPIO_4_PIN_CTRL
| P05_GPIO_5_PIN_CTRL
#if !(FB_SWD)
| P06_GPIO_6_PIN_CTRL
| P07_GPIO_7_PIN_CTRL
#else
| P06_SW_DAT_PIN_CTRL
| P07_SW_CLK_PIN_CTRL
#endif
| P10_GPIO_8_PIN_CTRL
| P11_GPIO_9_PIN_CTRL
| P12_GPIO_10_PIN_CTRL
| P13_GPIO_11_PIN_CTRL
| P14_GPIO_12_PIN_CTRL
| P15_GPIO_13_PIN_CTRL
| P16_GPIO_14_PIN_CTRL
| P17_UART0_RXD_PIN_CTRL
);
syscon_SetPMCR1(QN_SYSCON, P20_GPIO_16_PIN_CTRL
| P21_GPIO_17_PIN_CTRL
| P22_GPIO_18_PIN_CTRL
| P23_I2C_SDA_PIN_CTRL
| P24_I2C_SCL_PIN_CTRL
| P25_GPIO_21_PIN_CTRL
| P26_PWM1_PIN_CTRL
| P27_GPIO_23_PIN_CTRL
#if !defined(CFG_JOYSTICK)
| P30_GPIO_24_PIN_CTRL
#else
| P30_AIN0_PIN_CTRL
#endif
| P31_GPIO_25_PIN_CTRL
#if (defined(CFG_HCI_SPI))
| P32_SPI0_DIN_PIN_CTRL //P3.2 spi1 data in
| P33_SPI0_DAT_PIN_CTRL //P3.3 spi1 data out
| P34_SPI0_CLK_PIN_CTRL //P3.4 spi1 clk
| P35_SPI0_CS0_PIN_CTRL //P3.5 spi1 cs
#else
| P32_GPIO_26_PIN_CTRL
| P33_GPIO_27_PIN_CTRL
| P34_GPIO_28_PIN_CTRL
| P35_GPIO_29_PIN_CTRL
#endif
| P36_GPIO_30_PIN_CTRL
);
// pin select
syscon_SetPMCR2(QN_SYSCON, SYSCON_MASK_UART1_PIN_SEL | SYSCON_MASK_SPI0_PIN_SEL);
// driver ability
syscon_SetPDCR(QN_SYSCON, 0x0); // 0 : low driver, 1 : high driver
// pin pull ( 00 : High-Z, 01 : Pull-down, 10 : Pull-up, 11 : Reserved )
#if defined(QN_EXT_FLASH)
// If external flash is used, P1.0~P1.3 should be Pull down for preventing leakage.
syscon_SetPPCR0(QN_SYSCON, 0xAA555AAA);
#else
#if (FB_SWD)
syscon_SetPPCR0(QN_SYSCON, 0xAAAA5AAA);
#else
syscon_SetPPCR0(QN_SYSCON, 0xAAAAAAAA);
#endif
#endif
syscon_SetPPCR1(QN_SYSCON, 0x2AAAAAAA);
}
/**
****************************************************************************************
* @brief GPIO functionn configuration.
*
* Set Pins as gpio pin or function pin
*****************************************************************************************
*/
void SystemIOCfg(void)
{
// P0.0 -> UART0 [TX] Pull Up Drive ability: Low
// P0.1 -> GPIO Pull Up Drive ability: Low
// P0.2 -> GPIO Pull Up Drive ability: Low
// P0.3 -> GPIO Pull Up Drive ability: Low
// P0.4 -> GPIO Pull Up Drive ability: Low
// P0.5 -> GPIO Pull Up Drive ability: Low
// P0.6 -> SWD [DAT] Pull Up Drive ability: Low
// P0.7 -> SWD [CLK] Pull Up Drive ability: Low
// P1.0 -> UART1 [RX] Pull Up Drive ability: Low
// P1.1 -> UART1 [TX] Pull Up Drive ability: Low
// P1.2 -> GPIO Pull Up Drive ability: Low
// P1.3 -> GPIO Pull Up Drive ability: Low
// P1.4 -> GPIO Pull Up Drive ability: Low
// P1.5 -> GPIO Pull Up Drive ability: Low
// P1.6 -> GPIO Pull Up Drive ability: Low
// P1.7 -> UART0 [RX] Pull Up Drive ability: Low
// P2.0 -> GPIO Pull Up Drive ability: Low
// P2.1 -> GPIO Pull Up Drive ability: Low
// P2.2 -> GPIO Pull Up Drive ability: Low
// P2.3 -> I2C [SDA] Pull Up Drive ability: Low
// P2.4 -> I2C [SCL] Pull Up Drive ability: Low
// P2.5 -> GPIO Pull Up Drive ability: Low
// P2.6 -> GPIO Pull Up Drive ability: Low
// P2.7 -> GPIO Pull Up Drive ability: Low
// P3.0 -> GPIO Pull Up Drive ability: Low
// P3.1 -> GPIO Pull Up Drive ability: Low
// P3.2 -> GPIO Pull Up Drive ability: Low
// P3.3 -> GPIO Pull Up Drive ability: Low
// P3.4 -> GPIO Pull Up Drive ability: Low
// P3.5 -> GPIO Pull Up Drive ability: Low
// P3.6 -> GPIO Pull Up Drive ability: Low
//Pin Mux Control Register
syscon_SetPMCR0(QN_SYSCON, P00_UART0_TXD_PIN_CTRL
| P01_GPIO_1_PIN_CTRL
| P02_GPIO_2_PIN_CTRL
| P03_GPIO_3_PIN_CTRL
| P04_GPIO_4_PIN_CTRL
| P05_GPIO_5_PIN_CTRL
| P06_SW_DAT_PIN_CTRL
| P07_SW_CLK_PIN_CTRL
| P10_UART1_RXD_PIN_CTRL
| P11_UART1_TXD_PIN_CTRL
| P12_GPIO_10_PIN_CTRL
| P13_GPIO_11_PIN_CTRL
| P14_GPIO_12_PIN_CTRL
| P15_GPIO_13_PIN_CTRL
| P16_GPIO_14_PIN_CTRL
| P17_UART0_RXD_PIN_CTRL);
//Pin Mux Control Register
syscon_SetPMCR2(QN_SYSCON, 0);
//Pin Mux Control Register
syscon_SetPMCR1(QN_SYSCON, P20_GPIO_16_PIN_CTRL
| P21_GPIO_17_PIN_CTRL
| P22_GPIO_18_PIN_CTRL
| P23_I2C_SDA_PIN_CTRL
| P24_I2C_SCL_PIN_CTRL
| P25_GPIO_21_PIN_CTRL
| P26_GPIO_22_PIN_CTRL
| P27_GPIO_23_PIN_CTRL
| P30_GPIO_24_PIN_CTRL
| P31_GPIO_25_PIN_CTRL
| P32_GPIO_26_PIN_CTRL
| P33_GPIO_27_PIN_CTRL
| P34_GPIO_28_PIN_CTRL
| P35_GPIO_29_PIN_CTRL
| P36_GPIO_30_PIN_CTRL);
//P23_I2C_SDA_PIN_CTRL
//P24_I2C_SCL_PIN_CTRL
//Pull Control Register
syscon_SetPPCR0(QN_SYSCON, 0xAAAAAAAA);
//Pull Control Register
syscon_SetPPCR1(QN_SYSCON, 0xAAAAAAAA);
//Drive ability Control Register
syscon_SetPDCR(QN_SYSCON, 0x00000000);
}
/*
****************************************************************************************
* @brief Test gpio work status
*
*****************************************************************************************/
void all_gpio_test(void)
{
// pin mux
syscon_SetPMCR0(QN_SYSCON, P00_UART0_TXD_PIN_CTRL
| P01_GPIO_1_PIN_CTRL
| P02_GPIO_2_PIN_CTRL
| P03_GPIO_3_PIN_CTRL
| P04_GPIO_4_PIN_CTRL
| P05_GPIO_5_PIN_CTRL
| P06_GPIO_6_PIN_CTRL
| P07_GPIO_7_PIN_CTRL
| P10_GPIO_8_PIN_CTRL
| P11_GPIO_9_PIN_CTRL
| P12_GPIO_10_PIN_CTRL
| P13_GPIO_11_PIN_CTRL
| P14_GPIO_12_PIN_CTRL
| P15_GPIO_13_PIN_CTRL
| P16_GPIO_14_PIN_CTRL
| P17_GPIO_15_PIN_CTRL
);
syscon_SetPMCR1(QN_SYSCON, P20_GPIO_16_PIN_CTRL
| P21_GPIO_17_PIN_CTRL
| P22_GPIO_18_PIN_CTRL
| P23_GPIO_19_PIN_CTRL
| P24_GPIO_20_PIN_CTRL
| P25_GPIO_21_PIN_CTRL
| P26_GPIO_22_PIN_CTRL
| P27_GPIO_23_PIN_CTRL
| P30_GPIO_24_PIN_CTRL
| P31_GPIO_25_PIN_CTRL
| P32_GPIO_26_PIN_CTRL
| P33_GPIO_27_PIN_CTRL
| P34_GPIO_28_PIN_CTRL
| P35_GPIO_29_PIN_CTRL
| P36_GPIO_30_PIN_CTRL
);
// driver ability
syscon_SetPDCR(QN_SYSCON, 0x0); // 0 : low driver, 1 : high driver
// pin pull ( 00 : High-Z, 01 : Pull-down, 10 : Pull-up, 11 : Reserved )
syscon_SetPPCR0(QN_SYSCON, 0xAAAAAAAA);
syscon_SetPPCR1(QN_SYSCON, 0xAAAAAAAA);
gpio_init(gpio_interrupt_callback);
gpio_set_direction_field(TEST_PIN,(uint32_t)GPIO_OUTPUT);
gpio_write_pin_field(TEST_PIN,(uint32_t)GPIO_LOW);
delay_5();
gpio_write_pin_field(TEST_PIN,(uint32_t)GPIO_HIGH);
delay_5();
gpio_write_pin_field(TEST_PIN,(uint32_t)GPIO_LOW);
delay_5();
gpio_write_pin_field(TEST_PIN,(uint32_t)GPIO_HIGH);
delay_5();
gpio_write_pin_field(TEST_PIN,(uint32_t)GPIO_LOW);
delay_5();
gpio_write_pin_field(TEST_PIN,(uint32_t)GPIO_HIGH);
delay_5();
gpio_write_pin_field(TEST_PIN,(uint32_t)GPIO_LOW);
delay_5();
gpio_write_pin_field(TEST_PIN,(uint32_t)GPIO_HIGH);
delay_5();
}
int main (void)
{
SystemInit();
#if 0
if (0x00000004 & inp32(0x40000038)) {
outp32(0x40000038, 0x80000000);
}
else {
Led_flash();
while(1);
}
#endif
/* Initialize GPIO */
gpio_init(cb_gpio);
#if TEST_SLEEP_NORMAL == TRUE
// --------------------------------------------
// sleep wakeup
// --------------------------------------------
//set all pin to gpio
syscon_SetPMCR0(QN_SYSCON, 0x00000000);
syscon_SetPMCR1(QN_SYSCON, 0x00000000);
//set all gpio input
gpio_set_direction_field(GPIO_PIN_ALL, GPIO_INPUT);
gpio_write_pin_field(GPIO_PIN_ALL, (uint32_t)GPIO_HIGH);
// pin pull ( 00 : High-Z, 01 : Pull-down, 10 : Pull-up, 11 : Reserved )
syscon_SetPPCR0(QN_SYSCON, 0xAAAA5AAA); // SWD pull-down save 20uA
syscon_SetPPCR1(QN_SYSCON, 0x2AAAAAAA);
// power down BUCK needed
syscon_SetIvrefX32WithMask(QN_SYSCON, SYSCON_MASK_BUCK_BYPASS|SYSCON_MASK_BUCK_DPD, MASK_ENABLE);
// power down Flash
syscon_SetPGCR2WithMask(QN_SYSCON, SYSCON_MASK_FLASH_VCC_EN, MASK_DISABLE);
// enable dbg power down
syscon_SetPGCR2WithMask(QN_SYSCON, SYSCON_MASK_DBGPMUENABLE, MASK_ENABLE);
// dis sar adc buffer
syscon_SetPGCR1WithMask(QN_SYSCON, SYSCON_MASK_DIS_SAR_BUF, MASK_ENABLE);
Led_flash();
do {
delay(10);
} while (gpio_read_pin(GPIO_P14) == GPIO_HIGH);
sleep_init();
wakeup_by_sleep_timer(__32K_TYPE);
wakeup_by_gpio(GPIO_P15, GPIO_WKUP_BY_LOW);
do {
gpio_set_direction(GPIO_P01, GPIO_INPUT);
//enter_sleep(SLEEP_NORMAL, WAKEUP_BY_GPIO, Led_flash);
if (wakeup_from_sleeptimer) {
sleep_timer_set(32000);
wakeup_from_sleeptimer = 0;
#if QN_32K_RCO == TRUE
clock_32k_correction_enable(clock_32k_correction_cb);
#endif
}
#if QN_32K_RCO == TRUE
if (gpio_sleep_allowed() && !dev_get_bf())
#else
if (gpio_sleep_allowed())
#endif
enter_sleep(SLEEP_NORMAL, WAKEUP_BY_OSC_EN|WAKEUP_BY_GPIO, Led_flash);
} while(1);
#endif
#if TEST_SLEEP_DEEP == TRUE
// --------------------------------------------
// deep sleep wakeup
// --------------------------------------------
//set all pin to gpio
syscon_SetPMCR0(QN_SYSCON, 0x00000000);
syscon_SetPMCR1(QN_SYSCON, 0x00000000);
//set all gpio input
gpio_set_direction_field(GPIO_PIN_ALL, (uint32_t)GPIO_INPUT);
gpio_write_pin_field(GPIO_PIN_ALL, (uint32_t)GPIO_HIGH);
// pin pull ( 00 : High-Z, 01 : Pull-down, 10 : Pull-up, 11 : Reserved )
syscon_SetPPCR0(QN_SYSCON, 0xAAAA5AAA); // SWD pull-down save 20uA
syscon_SetPPCR1(QN_SYSCON, 0x2AAAAAAA);
// power down BUCK needed
syscon_SetIvrefX32WithMask(QN_SYSCON, SYSCON_MASK_BUCK_BYPASS|SYSCON_MASK_BUCK_DPD, MASK_ENABLE);
// power down Flash
syscon_SetPGCR2WithMask(QN_SYSCON, SYSCON_MASK_FLASH_VCC_EN, MASK_DISABLE);
// enable dbg power down
syscon_SetPGCR2WithMask(QN_SYSCON, SYSCON_MASK_DBGPMUENABLE, MASK_ENABLE);
// dis sar adc buffer
syscon_SetPGCR1WithMask(QN_SYSCON, SYSCON_MASK_DIS_SAR_BUF, MASK_ENABLE);
Led_flash();
do {
delay(10);
} while (gpio_read_pin(GPIO_P14) == GPIO_HIGH);
sleep_init();
do {
gpio_set_direction(GPIO_P01, GPIO_INPUT);
wakeup_by_gpio(GPIO_P15, GPIO_WKUP_BY_CHANGE);
enter_sleep(SLEEP_DEEP, WAKEUP_BY_GPIO, Led_flash);
} while(1);
#endif
#if TEST_SLEEP_CPU_CLK_OFF == TRUE
// --------------------------------------------
// clock gating
// --------------------------------------------
// Set timer 0 wakeup
timer_init(QN_TIMER0, NULL);
timer_config(QN_TIMER0, TIMER_PSCAL_DIV, TIMER_COUNT_MS(1000, TIMER_PSCAL_DIV));
timer_enable(QN_TIMER0, MASK_ENABLE);
sleep_init();
do {
enter_sleep(SLEEP_CPU_CLK_OFF, WAKEUP_BY_TIMER0, NULL);
Led_flash();
}
while(1);
#endif
}