static void lpc_task_disable_irq(void){
task_disable_irq(NPCX_IRQ_SHM);
task_disable_irq(NPCX_IRQ_KBC_IBF);
task_disable_irq(NPCX_IRQ_PM_CHAN_IBF);
task_disable_irq(NPCX_IRQ_PORT80);
}
int sps_unregister_rx_handler(void)
{
if (!sps_rx_handler)
return -1;
task_disable_irq(GC_IRQNUM_SPS0_RXFIFO_LVL_INTR);
task_disable_irq(GC_IRQNUM_SPS0_CS_DEASSERT_INTR);
sps_rx_handler = NULL;
return 0;
}
static void ext_timer_ctrl(enum ext_timer_sel ext_timer,
enum ext_timer_clock_source ext_timer_clock,
int start,
int with_int,
int32_t count)
{
uint8_t intc_mask;
/* rising-edge-triggered */
intc_mask = et_ctrl_regs[ext_timer].mask;
*et_ctrl_regs[ext_timer].mode |= intc_mask;
*et_ctrl_regs[ext_timer].polarity &= ~intc_mask;
/* clear interrupt status */
task_clear_pending_irq(et_ctrl_regs[ext_timer].irq);
/* These bits control the clock input source to the exttimer 3 - 8 */
IT83XX_ETWD_ETXPSR(ext_timer) = ext_timer_clock;
/* The count number of external timer n. */
IT83XX_ETWD_ETXCNTLR(ext_timer) = count;
ext_timer_stop(ext_timer, 0);
if (start)
ext_timer_start(ext_timer, 0);
if (with_int)
task_enable_irq(et_ctrl_regs[ext_timer].irq);
else
task_disable_irq(et_ctrl_regs[ext_timer].irq);
}
/* Irq for hwtimer event */
void __hw_clock_event_irq(void)
{
/* ITIM event module disable */
CLEAR_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
/* Disable interrupt of event */
task_disable_irq(ITIM16_INT(ITIM_EVENT_NO));
/* Clear timeout status for event */
SET_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_TO_STS);
/* Clear event parameters */
evt_expired_us = 0;
evt_cnt = 0;
/* handle upper driver */
process_timers(0);
#ifdef CONFIG_LOW_POWER_IDLE
/*
* Set event for ITIM32 after process_timers() since no events set if
* event's deadline is over 32 bits but current source clock isn't.
* ITIM32 is based on apb2 and ec won't wake-up in deep-idle even if it
* expires.
*/
if (evt_expired_us == 0)
__hw_clock_event_set(EVT_MAX_EXPIRED_US);
#endif
}
void lpc_kbc_obf_interrupt(void){
/* reserve for future handle */
if (!IS_BIT_SET(NPCX_HICTRL, 0)) {
SET_BIT(NPCX_HICTRL, 0); /* back to H/W control of IRQ1 */
CLEAR_BIT(NPCX_HIIRQC, 0); /* back to default of IRQB1 */
}
task_disable_irq(NPCX_IRQ_KBC_OBF);
}
void ext_timer_stop(enum ext_timer_sel ext_timer, int dis_irq)
{
/* disable external timer n */
IT83XX_ETWD_ETXCTRL(ext_timer) &= ~0x01;
if (dis_irq)
task_disable_irq(et_ctrl_regs[ext_timer].irq);
}
void dma_disable_tc_interrupt(enum dma_channel channel)
{
stm32_dma_chan_t *chan = dma_get_channel(channel);
id[channel] = TASK_ID_INVALID;
chan->ccr &= ~STM32_DMA_CCR_TCIE;
task_disable_irq(dma_get_irq(channel));
}
/* KB controller output buffer empty ISR */
void lpc_kbc_obe_interrupt(void)
{
/* Disable KBC OBE interrupt */
CLEAR_BIT(NPCX_HICTRL, NPCX_HICTRL_OBECIE);
task_disable_irq(NPCX_IRQ_KBC_OBE);
CPRINTS("obe isr %02x", NPCX_HIKMST);
task_wake(TASK_ID_KEYPROTO);
}
void keyboard_raw_enable_interrupt(int enable)
{
if (enable) {
task_clear_pending_irq(MEC1322_IRQ_KSC_INT);
task_enable_irq(MEC1322_IRQ_KSC_INT);
} else {
task_disable_irq(MEC1322_IRQ_KSC_INT);
}
}
void dma_disable_tc_interrupt(enum dma_channel stream)
{
stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
dma_stream->scr &= ~STM32_DMA_CCR_TCIE;
task_disable_irq(dma_get_irq(stream));
dma_irq[stream].cb = NULL;
dma_irq[stream].cb_data = NULL;
}
int gpio_disable_interrupt(enum gpio_signal signal)
{
int irq = gpio_to_irq(gpio_list[signal].port, gpio_list[signal].mask);
if (irq == -1)
return EC_ERROR_UNKNOWN;
else
task_disable_irq(irq);
return EC_SUCCESS;
}
/* Cancel the next event programmed by __hw_clock_event_set */
void __hw_clock_event_clear(void)
{
/* ITIM event module disable */
CLEAR_BIT(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_ITEN);
/* Disable interrupt of Event */
task_disable_irq(ITIM16_INT(ITIM_EVENT_NO));
/* Clear event parameters */
evt_expired_us = 0;
evt_cnt = 0;
}
static void lpc_send_response_packet(struct host_packet *pkt)
{
/* Ignore in-progress on LPC since interface is synchronous anyway */
if (pkt->driver_result == EC_RES_IN_PROGRESS)
return;
/* Write result to the data byte. This sets the TOH status bit. */
LPC_POOL_CMD[1] = pkt->driver_result;
/* Clear the busy bit, so the host knows the EC is done. */
task_disable_irq(LM4_IRQ_LPC);
LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_BUSY;
task_enable_irq(LM4_IRQ_LPC);
}
void usb_release(void)
{
/* signal disconnect to host */
usb_disconnect();
/* disable interrupt handlers */
task_disable_irq(GC_IRQNUM_USB0_USBINTR);
/* disable clocks */
clock_enable_module(MODULE_USB, 0);
/* TODO: pin-mux */
/* USB is off, so sleep whenever */
enable_sleep(SLEEP_MASK_USB_DEVICE);
}
void lpc_kbc_obe_interrupt(void)
{
task_disable_irq(IT83XX_IRQ_KBC_OUT);
task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
if (!(IT83XX_KBC_KBHICR & 0x01)) {
IT83XX_KBC_KBIRQR &= ~0x01;
IT83XX_KBC_KBHICR |= 0x01;
}
#ifdef HAS_TASK_KEYPROTO
task_wake(TASK_ID_KEYPROTO);
#endif
}
void i2c_interrupt(int port)
{
int id = pdata[port].task_waiting;
/* Clear the interrupt status */
task_clear_pending_irq(i2c_ctrl_regs[port].irq);
/* If no task is waiting, just return */
if (id == TASK_ID_INVALID)
return;
/* If done doing work, wake up the task waiting for the transfer */
if (!i2c_transaction(port)) {
task_disable_irq(i2c_ctrl_regs[port].irq);
task_set_event(id, TASK_EVENT_I2C_IDLE, 0);
}
}
enum cts_rc test_task_disable_irq(void)
{
uint32_t event;
wake_me_up = 1;
task_disable_irq(CTS_IRQ_NUMBER);
/* Sleep and wait for interrupt. This should time out. */
event = task_wait_event(CTS_INTERRUPT_TRIGGER_DELAY_US * 2);
if (event != TASK_EVENT_TIMER) {
CPRINTS("Woken up by unexpected event: 0x%08x", event);
return CTS_RC_FAILURE;
}
task_enable_irq(CTS_IRQ_NUMBER);
return CTS_RC_SUCCESS;
}
static void lpc_send_response(struct host_cmd_handler_args *args)
{
uint8_t *out;
int size = args->response_size;
int csum;
int i;
/* Ignore in-progress on LPC since interface is synchronous anyway */
if (args->result == EC_RES_IN_PROGRESS)
return;
/* Handle negative size */
if (size < 0) {
args->result = EC_RES_INVALID_RESPONSE;
size = 0;
}
/* New-style response */
lpc_host_args->flags =
(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
EC_HOST_ARGS_FLAG_TO_HOST;
lpc_host_args->data_size = size;
csum = args->command + lpc_host_args->flags +
lpc_host_args->command_version +
lpc_host_args->data_size;
for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
csum += *out;
lpc_host_args->checksum = (uint8_t)csum;
/* Fail if response doesn't fit in the param buffer */
if (size > EC_PROTO2_MAX_PARAM_SIZE)
args->result = EC_RES_INVALID_RESPONSE;
/* Write result to the data byte. This sets the TOH status bit. */
LPC_POOL_CMD[1] = args->result;
/* Clear the busy bit, so the host knows the EC is done. */
task_disable_irq(LM4_IRQ_LPC);
LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_BUSY;
task_enable_irq(LM4_IRQ_LPC);
}
static void handle_interrupt(int port)
{
int id = task_waiting_on_port[port];
/* Clear the interrupt status */
MEC1322_I2C_COMPLETE(port) |= 1 << 29;
/*
* Write to control register interferes with I2C transaction.
* Instead, let's disable IRQ from the core until the next time
* we want to wait for STS_PIN/STS_NBB.
*/
task_disable_irq(MEC1322_IRQ_I2C_0 + port);
/* Wake up the task which was waiting on the I2C interrupt, if any. */
if (id != TASK_ID_INVALID)
task_set_event(id, TASK_EVENT_I2C_IDLE, 0);
}
void usb_release(void)
{
/* signal disconnect to host */
usb_disconnect();
/* disable interrupt handlers */
task_disable_irq(GC_IRQNUM_USB0_USBINTR);
/* Deactivate the PHY */
GR_USB_GGPIO = GGPIO_WRITE(USB_CUSTOM_CFG_REG, 0);
/* disable clocks */
clock_enable_module(MODULE_USB, 0);
/* TODO: pin-mux */
/* USB is off, so sleep whenever */
enable_sleep(SLEEP_MASK_USB_DEVICE);
}
static void update_host_event_status(void)
{
int need_sci = 0;
int need_smi = 0;
if (!init_done)
return;
/* Disable PMC1 interrupt while updating status register */
task_disable_irq(IT83XX_IRQ_PMC_IN);
if (host_events & event_mask[LPC_HOST_EVENT_SMI]) {
/* Only generate SMI for first event */
if (!(pm_get_status(LPC_ACPI_CMD) & EC_LPC_STATUS_SMI_PENDING))
need_smi = 1;
pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SMI_PENDING, 1);
} else {
pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SMI_PENDING, 0);
}
if (host_events & event_mask[LPC_HOST_EVENT_SCI]) {
/* Generate SCI for every event */
need_sci = 1;
pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SCI_PENDING, 1);
} else {
pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SCI_PENDING, 0);
}
/* Copy host events to mapped memory */
*(uint32_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) = host_events;
task_enable_irq(IT83XX_IRQ_PMC_IN);
/* Process the wake events. */
lpc_update_wake(host_events & event_mask[LPC_HOST_EVENT_WAKE]);
/* Send pulse on SMI signal if needed */
if (need_smi)
lpc_generate_smi();
/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
if (need_sci)
lpc_generate_sci();
}
/**
* Update the host event status.
*
* Sends a pulse if masked event status becomes non-zero:
* - SMI pulse via EC_SMI_L GPIO
* - SCI pulse via LPC0SCI
*/
static void update_host_event_status(void)
{
int need_sci = 0;
int need_smi = 0;
if (!init_done)
return;
/* Disable LPC interrupt while updating status register */
task_disable_irq(LM4_IRQ_LPC);
if (host_events & event_mask[LPC_HOST_EVENT_SMI]) {
/* Only generate SMI for first event */
if (!(LM4_LPC_ST(LPC_CH_ACPI) & LM4_LPC_ST_SMI))
need_smi = 1;
LM4_LPC_ST(LPC_CH_ACPI) |= LM4_LPC_ST_SMI;
} else
LM4_LPC_ST(LPC_CH_ACPI) &= ~LM4_LPC_ST_SMI;
if (host_events & event_mask[LPC_HOST_EVENT_SCI]) {
/* Generate SCI for every event */
need_sci = 1;
LM4_LPC_ST(LPC_CH_ACPI) |= LM4_LPC_ST_SCI;
} else
LM4_LPC_ST(LPC_CH_ACPI) &= ~LM4_LPC_ST_SCI;
/* Copy host events to mapped memory */
*(uint32_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) = host_events;
task_enable_irq(LM4_IRQ_LPC);
/* Process the wake events. */
lpc_update_wake(host_events & event_mask[LPC_HOST_EVENT_WAKE]);
/* Send pulse on SMI signal if needed */
if (need_smi)
lpc_generate_smi();
/* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */
if (need_sci)
lpc_generate_sci();
}
static void lpc_task_disable_irq(void)
{
task_disable_irq(NPCX_IRQ_KBC_IBF);
task_disable_irq(NPCX_IRQ_PM_CHAN_IBF);
task_disable_irq(NPCX_IRQ_PORT80);
#ifdef CONFIG_ESPI
task_disable_irq(NPCX_IRQ_ESPI);
/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
task_disable_irq(NPCX_IRQ_WKINTA_2);
/* Virtual Wire: HOST_RST_WARN,SUS_WARN, SUS_PWRDN_ACK, SLP_A */
task_disable_irq(NPCX_IRQ_WKINTB_2);
/* Disable eSPI module interrupts */
NPCX_ESPIIE &= ~(ESPIIE_GENERIC | ESPIIE_VW);
#endif
}
int chip_i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_size,
uint8_t *in, int in_size, int flags)
{
struct i2c_port_data *pd = pdata + port;
uint32_t events = 0;
if (out_size == 0 && in_size == 0)
return EC_SUCCESS;
if (pd->i2ccs) {
if ((flags & I2C_XFER_SINGLE) == I2C_XFER_SINGLE)
flags &= ~I2C_XFER_START;
}
/* Copy data to port struct */
pd->out = out;
pd->out_size = out_size;
pd->in = in;
pd->in_size = in_size;
pd->flags = flags;
pd->widx = 0;
pd->ridx = 0;
pd->err = 0;
pd->addr = slave_addr;
if (port < I2C_STANDARD_PORT_COUNT) {
/* Make sure we're in a good state to start */
if ((flags & I2C_XFER_START) && (i2c_is_busy(port)
|| (IT83XX_SMB_HOSTA(port) & HOSTA_ALL_WC_BIT)
|| (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
/* Attempt to unwedge the port. */
i2c_unwedge(port);
/* reset i2c port */
i2c_reset(port, I2C_RC_NO_IDLE_FOR_START);
}
} else {
/* Make sure we're in a good state to start */
if ((flags & I2C_XFER_START) && (i2c_is_busy(port)
|| (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
/* Attempt to unwedge the port. */
i2c_unwedge(port);
/* reset i2c port */
i2c_reset(port, I2C_RC_NO_IDLE_FOR_START);
}
}
pd->task_waiting = task_get_current();
if (pd->flags & I2C_XFER_START) {
pd->i2ccs = I2C_CH_NORMAL;
/* enable i2c interrupt */
task_clear_pending_irq(i2c_ctrl_regs[port].irq);
task_enable_irq(i2c_ctrl_regs[port].irq);
}
/* Start transaction */
i2c_transaction(port);
/* Wait for transfer complete or timeout */
events = task_wait_event_mask(TASK_EVENT_I2C_IDLE, pd->timeout_us);
/* disable i2c interrupt */
task_disable_irq(i2c_ctrl_regs[port].irq);
pd->task_waiting = TASK_ID_INVALID;
/* Handle timeout */
if (!(events & TASK_EVENT_I2C_IDLE)) {
pd->err = EC_ERROR_TIMEOUT;
/* reset i2c port */
i2c_reset(port, I2C_RC_TIMEOUT);
}
/* reset i2c channel status */
if (pd->err)
pd->i2ccs = I2C_CH_NORMAL;
return pd->err;
}
void system_hibernate(uint32_t seconds, uint32_t microseconds)
{
int i;
#ifdef CONFIG_HOSTCMD_PD
/* Inform the PD MCU that we are going to hibernate. */
host_command_pd_request_hibernate();
/* Wait to ensure exchange with PD before hibernating. */
msleep(100);
#endif
cflush();
if (board_hibernate)
board_hibernate();
/* Disable interrupts */
interrupt_disable();
for (i = 0; i <= 92; ++i) {
task_disable_irq(i);
task_clear_pending_irq(i);
}
for (i = 8; i <= 23; ++i)
MEC1322_INT_DISABLE(i) = 0xffffffff;
MEC1322_INT_BLK_DIS |= 0xffff00;
/* Power down ADC VREF */
MEC1322_EC_ADC_VREF_PD |= 1;
/* Assert nSIO_RESET */
MEC1322_PCR_PWR_RST_CTL |= 1;
/* Disable UART */
MEC1322_UART_ACT &= ~0x1;
MEC1322_LPC_ACT &= ~0x1;
/* Disable JTAG */
MEC1322_EC_JTAG_EN &= ~1;
/* Disable 32KHz clock */
MEC1322_VBAT_CE &= ~0x2;
/* Stop watchdog */
MEC1322_WDG_CTL &= ~1;
/* Stop timers */
MEC1322_TMR32_CTL(0) &= ~1;
MEC1322_TMR32_CTL(1) &= ~1;
MEC1322_TMR16_CTL(0) &= ~1;
/* Power down ADC */
MEC1322_ADC_CTRL &= ~1;
/* Disable blocks */
MEC1322_PCR_CHIP_SLP_EN |= 0x3;
MEC1322_PCR_EC_SLP_EN |= MEC1322_PCR_EC_SLP_EN_SLEEP;
MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP;
MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP;
MEC1322_PCR_SLOW_CLK_CTL &= 0xfffffc00;
/* Set sleep state */
MEC1322_PCR_SYS_SLP_CTL = (MEC1322_PCR_SYS_SLP_CTL & ~0x7) | 0x2;
CPU_SCB_SYSCTRL |= 0x4;
/* Setup GPIOs for hibernate */
if (board_hibernate_late)
board_hibernate_late();
#ifdef CONFIG_USB_PD_PORT_COUNT
/*
* Leave USB-C charging enabled in hibernate, in order to
* allow wake-on-plug. 5V enable must be pulled low.
*/
#if CONFIG_USB_PD_PORT_COUNT > 0
gpio_set_flags(GPIO_USB_C0_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 0);
#endif
#if CONFIG_USB_PD_PORT_COUNT > 1
gpio_set_flags(GPIO_USB_C1_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 0);
#endif
#endif /* CONFIG_USB_PD_PORT_COUNT */
if (hibernate_wake_pins_used > 0) {
for (i = 0; i < hibernate_wake_pins_used; ++i) {
const enum gpio_signal pin = hibernate_wake_pins[i];
gpio_reset(pin);
gpio_enable_interrupt(pin);
}
interrupt_enable();
task_enable_irq(MEC1322_IRQ_GIRQ8);
task_enable_irq(MEC1322_IRQ_GIRQ9);
task_enable_irq(MEC1322_IRQ_GIRQ10);
task_enable_irq(MEC1322_IRQ_GIRQ11);
task_enable_irq(MEC1322_IRQ_GIRQ20);
}
if (seconds || microseconds) {
MEC1322_INT_BLK_EN |= 1 << 17;
MEC1322_INT_ENABLE(17) |= 1 << 20;
interrupt_enable();
task_enable_irq(MEC1322_IRQ_HTIMER);
if (seconds > 2) {
ASSERT(seconds <= 0xffff / 8);
MEC1322_HTIMER_CONTROL = 1;
MEC1322_HTIMER_PRELOAD =
(seconds * 8 + microseconds / 125000);
} else {
MEC1322_HTIMER_CONTROL = 0;
MEC1322_HTIMER_PRELOAD =
(seconds * 1000000 + microseconds) * 2 / 71;
}
}
asm("wfi");
/* Use 48MHz clock to speed through wake-up */
MEC1322_PCR_PROC_CLK_CTL = 1;
/* Reboot */
_system_reset(0, 1);
/* We should never get here. */
while (1)
;
}
/* Disable LPC ACPI-EC interrupts */
void lpc_disable_acpi_interrupts(void)
{
task_disable_irq(IT83XX_IRQ_PMC_IN);
}
static void lpc_init(void)
{
/*
* DLM 52k~56k size select enable.
* For mapping LPC I/O cycle 800h ~ 9FFh to DLM 8D800 ~ 8D9FF.
*/
IT83XX_GCTRL_MCCR2 |= 0x10;
IT83XX_GPIO_GCR = 0x06;
/* The register pair to access PNPCFG is 004Eh and 004Fh */
IT83XX_GCTRL_BADRSEL = 0x01;
/* Disable KBC IRQ */
IT83XX_KBC_KBIRQR = 0x00;
/*
* bit2, Output Buffer Empty CPU Interrupt Enable.
* bit3, Input Buffer Full CPU Interrupt Enable.
*/
IT83XX_KBC_KBHICR |= 0x0C;
/* PM1 Input Buffer Full Interrupt Enable for 62h/66 port */
pm_set_ctrl(LPC_ACPI_CMD, PM_CTRL_IBFIE, 1);
/* PM2 Input Buffer Full Interrupt Enable for 200h/204 port */
pm_set_ctrl(LPC_HOST_CMD, PM_CTRL_IBFIE, 1);
memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
memset(lpc_host_args, 0, sizeof(*lpc_host_args));
/* Host LPC I/O cycle mapping to RAM */
/*
* bit[4], H2RAM through LPC IO cycle.
* bit[1], H2RAM window 1 enabled.
* bit[0], H2RAM window 0 enabled.
*/
IT83XX_SMFI_HRAMWC |= 0x13;
/*
* bit[7:6]
* Host RAM Window[x] Read Protect Enable
* 00b: Disabled
* 01b: Lower half of RAM window protected
* 10b: Upper half of RAM window protected
* 11b: All protected
*
* bit[5:4]
* Host RAM Window[x] Write Protect Enable
* 00b: Disabled
* 01b: Lower half of RAM window protected
* 10b: Upper half of RAM window protected
* 11b: All protected
*
* bit[2:0]
* Host RAM Window 1 Size (HRAMW1S)
* 0h: 16 bytes
* 1h: 32 bytes
* 2h: 64 bytes
* 3h: 128 bytes
* 4h: 256 bytes
* 5h: 512 bytes
* 6h: 1024 bytes
* 7h: 2048 bytes
*/
/* H2RAM Win 0 Base Address 800h allow r/w for host_cmd_memmap */
IT83XX_SMFI_HRAMW0BA = 0x80;
IT83XX_SMFI_HRAMW0AAS = 0x04;
/* H2RAM Win 1 Base Address 900h allow r for acpi_ec_memmap */
IT83XX_SMFI_HRAMW1BA = 0x90;
IT83XX_SMFI_HRAMW1AAS = 0x34;
/* We support LPC args and version 3 protocol */
*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
EC_HOST_CMD_FLAG_VERSION_3;
/*
* bit[5], Dedicated interrupt
* INT3: PMC1 Output Buffer Empty Int
* INT25: PMC1 Input Buffer Full Int
* INT26: PMC2 Output Buffer Empty Int
* INT27: PMC2 Input Buffer Full Int
*/
IT83XX_PMC_MBXCTRL |= 0x20;
/* PM3 Input Buffer Full Interrupt Enable for 80h port */
pm_set_ctrl(LPC_HOST_PORT_80H, PM_CTRL_IBFIE, 1);
gpio_enable_interrupt(GPIO_PCH_PLTRST_L);
task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
task_disable_irq(IT83XX_IRQ_KBC_OUT);
task_clear_pending_irq(IT83XX_IRQ_KBC_IN);
task_enable_irq(IT83XX_IRQ_KBC_IN);
task_clear_pending_irq(IT83XX_IRQ_PMC_IN);
task_enable_irq(IT83XX_IRQ_PMC_IN);
task_clear_pending_irq(IT83XX_IRQ_PMC2_IN);
task_enable_irq(IT83XX_IRQ_PMC2_IN);
task_clear_pending_irq(IT83XX_IRQ_PMC3_IN);
task_enable_irq(IT83XX_IRQ_PMC3_IN);
/* Sufficiently initialized */
init_done = 1;
/* Update host events now that we can copy them to memmap */
update_host_event_status();
}
/* Disable LPC ACPI-EC0 interrupts */
void lpc_disable_acpi_interrupts(void)
{
task_disable_irq(MEC1322_IRQ_ACPIEC0_IBF);
}
void system_hibernate(uint32_t seconds, uint32_t microseconds)
{
int i;
cflush();
/* Disable interrupts */
interrupt_disable();
for (i = 0; i <= 92; ++i) {
task_disable_irq(i);
task_clear_pending_irq(i);
}
for (i = 8; i <= 23; ++i)
MEC1322_INT_DISABLE(i) = 0xffffffff;
MEC1322_INT_BLK_DIS |= 0xffff00;
/* Set processor clock to lowest, 1MHz */
MEC1322_PCR_PROC_CLK_CTL = 48;
/* Power down ADC VREF */
MEC1322_EC_ADC_VREF_PD |= 1;
/* Assert nSIO_RESET */
MEC1322_PCR_PWR_RST_CTL |= 1;
/* Disable UART */
MEC1322_UART_ACT &= ~0x1;
MEC1322_LPC_ACT &= ~0x1;
/* Disable JTAG */
MEC1322_EC_JTAG_EN &= ~1;
/* Disable 32KHz clock */
MEC1322_VBAT_CE &= ~0x2;
/* Stop watchdog */
MEC1322_WDG_CTL &= ~1;
/* Stop timers */
MEC1322_TMR32_CTL(0) &= ~1;
MEC1322_TMR32_CTL(1) &= ~1;
MEC1322_TMR16_CTL(0) &= ~1;
/* Power down ADC */
MEC1322_ADC_CTRL &= ~1;
/* Disable blocks */
MEC1322_PCR_CHIP_SLP_EN |= 0x3;
MEC1322_PCR_EC_SLP_EN |= 0xe0700ff7;
MEC1322_PCR_HOST_SLP_EN |= 0x5f003;
MEC1322_PCR_EC_SLP_EN2 |= 0x1ffffff8;
MEC1322_PCR_SYS_SLP_CTL = (MEC1322_PCR_SYS_SLP_CTL & ~0x7) | 0x2;
MEC1322_PCR_SLOW_CLK_CTL &= 0xfffffc00;
CPU_SCB_SYSCTRL |= 0x4;
system_unpower_gpio();
#ifdef CONFIG_WAKE_PIN
gpio_set_flags_by_mask(gpio_list[CONFIG_WAKE_PIN].port,
gpio_list[CONFIG_WAKE_PIN].mask,
gpio_list[CONFIG_WAKE_PIN].flags);
gpio_enable_interrupt(CONFIG_WAKE_PIN);
interrupt_enable();
task_enable_irq(MEC1322_IRQ_GIRQ8);
task_enable_irq(MEC1322_IRQ_GIRQ9);
task_enable_irq(MEC1322_IRQ_GIRQ10);
task_enable_irq(MEC1322_IRQ_GIRQ11);
task_enable_irq(MEC1322_IRQ_GIRQ20);
#endif
if (seconds || microseconds) {
MEC1322_INT_BLK_EN |= 1 << 17;
MEC1322_INT_ENABLE(17) |= 1 << 20;
interrupt_enable();
task_enable_irq(MEC1322_IRQ_HTIMER);
if (seconds > 2) {
ASSERT(seconds <= 0xffff / 8);
MEC1322_HTIMER_CONTROL = 1;
MEC1322_HTIMER_PRELOAD =
(seconds * 8 + microseconds / 125000);
} else {
MEC1322_HTIMER_CONTROL = 0;
MEC1322_HTIMER_PRELOAD =
(seconds * 1000000 + microseconds) * 2 / 71;
}
}
asm("wfi");
/* We lost states of most modules, let's just reboot */
_system_reset(0, 1);
}
static void usart_variant_disable(struct usart_config const *config)
{
task_disable_irq(config->hw->irq);
configs[config->hw->index] = NULL;
}