/**
* Configures the TC to generate output events at the sample frequency.
*
* Configures the TC in Frequency Generation mode, with an event output once
* each time the audio sample frequency period expires.
*/
void ZerodioClass::tcConfigure(uint32_t sampleRate)
{
// Enable GCLK for TCC2 and TC5 (timer counter input clock)
GCLK->CLKCTRL.reg = (uint16_t) (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_ID(GCM_TC4_TC5)) ;
while (GCLK->STATUS.bit.SYNCBUSY);
tcReset();
// Set Timer counter Mode to 16 bits
TC5->COUNT16.CTRLA.reg |= TC_CTRLA_MODE_COUNT16;
// Set TC5 mode as match frequency
TC5->COUNT16.CTRLA.reg |= TC_CTRLA_WAVEGEN_MFRQ;
TC5->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER_DIV1 | TC_CTRLA_ENABLE;
TC5->COUNT16.CC[0].reg = (uint16_t) (SystemCoreClock / sampleRate - 1);
while (tcIsSyncing());
// Configure interrupt request
NVIC_DisableIRQ(TC5_IRQn);
NVIC_ClearPendingIRQ(TC5_IRQn);
NVIC_SetPriority(TC5_IRQn, 0);
NVIC_EnableIRQ(TC5_IRQn);
// Enable the TC5 interrupt request
TC5->COUNT16.INTENSET.bit.MC0 = 1;
while (tcIsSyncing());
}
void ZerodioClass::tcReset()
{
// Reset TCx
TC5->COUNT16.CTRLA.reg = TC_CTRLA_SWRST;
while (tcIsSyncing());
while (TC5->COUNT16.CTRLA.bit.SWRST);
}
void ZerodioClass::tcStartCounter()
{
// Enable TC
TC5->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE;
while (tcIsSyncing());
}
void AudioFrequencyMeter::tcDisable()
{
// Disable TC5
TC5->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
while (tcIsSyncing())
;
}
void AudioFrequencyMeter::tcReset()
{
TC5->COUNT16.CTRLA.reg = TC_CTRLA_SWRST;
while (tcIsSyncing())
;
while (TC5->COUNT16.CTRLA.bit.SWRST)
;
}
void ZerodioClass::tcDisable()
{
// Disable TC5
TC5->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
while (tcIsSyncing());
}
void AudioFrequencyMeter::tcEnable()
{
TC5->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE;
while (tcIsSyncing())
;
}
