コード例 #1
0
ファイル: display.c プロジェクト: RowanLiu/ported_uboot
static void print_mode(const struct display_timing *timing)
{
	int refresh = tegra_dc_calc_refresh(timing);

	debug("MODE:%dx%d@%d.%03uHz pclk=%d\n",
	      timing->hactive.typ, timing->vactive.typ, refresh / 1000,
	      refresh % 1000, timing->pixelclock.typ);
}
コード例 #2
0
ファイル: display.c プロジェクト: RafaelRMachado/Coreboot
static void print_mode(const struct soc_nvidia_tegra124_config *config)
{
	if (config) {
		int refresh = tegra_dc_calc_refresh(config);
		printk(BIOS_ERR,
			"MODE:%dx%d@%d.%03uHz pclk=%d\n",
			config->xres, config->yres,
			refresh / 1000, refresh % 1000,
			config->pixel_clock);
	}
}
コード例 #3
0
static void print_mode(struct tegra_dc *dc,
			const struct tegra_dc_mode *mode, const char *note)
{
	if (mode) {
		int refresh = tegra_dc_calc_refresh(mode);
		dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
			note ? note : "",
			mode->h_active, mode->v_active,
			refresh / 1000, refresh % 1000,
			mode->pclk);
	}
}
コード例 #4
0
int tegra_dc_to_fb_videomode(struct fb_videomode *fbmode,
	const struct tegra_dc_mode *mode)
{
	long mode_pclk;

	if (!fbmode || !mode || !mode->pclk)
		return -EINVAL;
	if (mode->rated_pclk >= 1000) /* handle DSI one-shot modes */
		mode_pclk = mode->rated_pclk;
	else if (mode->pclk >= 1000) /* normal continous modes */
		mode_pclk = mode->pclk;
	else
		mode_pclk = 0;
	memset(fbmode, 0, sizeof(*fbmode));
	fbmode->right_margin = mode->h_front_porch;
	fbmode->lower_margin = mode->v_front_porch;
	fbmode->hsync_len = mode->h_sync_width;
	fbmode->vsync_len = mode->v_sync_width;
	fbmode->left_margin = mode->h_back_porch;
	fbmode->upper_margin = mode->v_back_porch;
	fbmode->xres = mode->h_active;
	fbmode->yres = mode->v_active;
	fbmode->vmode = FB_VMODE_NONINTERLACED;
	if (mode->stereo_mode) {
#ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
		/* Double the pixel clock and update v_active only for
		 * frame packed mode */
		mode_pclk /= 2;
		/* total v_active = yres*2 + activespace */
		fbmode->yres = (mode->v_active - mode->v_sync_width -
			mode->v_back_porch - mode->v_front_porch) / 2;
		fbmode->vmode |= FB_VMODE_STEREO_FRAME_PACK;
#else
		fbmode->vmode |= FB_VMODE_STEREO_LEFT_RIGHT;
#endif
	}

	if (!(mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC))
		fbmode->sync |=  FB_SYNC_HOR_HIGH_ACT;
	if (!(mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC))
		fbmode->sync |= FB_SYNC_VERT_HIGH_ACT;
	if (mode->avi_m == TEGRA_DC_MODE_AVI_M_16_9)
		fbmode->flag |= FB_FLAG_RATIO_16_9;
	else if (mode->avi_m == TEGRA_DC_MODE_AVI_M_4_3)
		fbmode->flag |= FB_FLAG_RATIO_4_3;

	if (mode_pclk >= 1000) /* else 0 */
		fbmode->pixclock = KHZ2PICOS(mode_pclk / 1000);
	fbmode->refresh = tegra_dc_calc_refresh(mode) / 1000;

	return 0;
}
コード例 #5
0
ファイル: mode.c プロジェクト: thoniorf/ouya_1_1-kernel
int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
{
	memcpy(&dc->mode, mode, sizeof(dc->mode));

	if (dc->out->type == TEGRA_DC_OUT_RGB)
		panel_sync_rate = tegra_dc_calc_refresh(mode);
	else if (dc->out->type == TEGRA_DC_OUT_DSI)
		panel_sync_rate = dc->out->dsi->rated_refresh_rate * 1000;

	print_mode(dc, mode, __func__);
	dc->frametime_ns = calc_frametime_ns(mode);

	return 0;
}