void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor) { u32 reg_val; struct display_controller *disp_ctrl = (void *)sor->dc->base; tegra_dc_sor_enable_dc(sor); tegra_dc_sor_config_panel(sor, 0); WRITEL(0x9f00, &disp_ctrl->cmd.state_ctrl); WRITEL(0x9f, &disp_ctrl->cmd.state_ctrl); WRITEL(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, &disp_ctrl->cmd.disp_pow_ctrl); reg_val = tegra_sor_readl(sor, NV_SOR_TEST); if (reg_val & NV_SOR_TEST_ATTACHED_TRUE) return; tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, NV_SOR_SUPER_STATE1_ATTACHED_NO); /* * Enable display2sor clock at least 2 cycles before DC start, * to clear sor internal valid signal. */ WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); WRITEL(0, &disp_ctrl->disp.disp_win_opt); WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); /* Attach head */ tegra_dc_sor_update(sor); tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, NV_SOR_SUPER_STATE1_ATTACHED_YES); tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, NV_SOR_SUPER_STATE1_ATTACHED_YES | NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE | NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL); tegra_dc_sor_super_update(sor); /* Enable dc */ reg_val = READL(&disp_ctrl->cmd.state_access); WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd); WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); WRITEL(reg_val, &disp_ctrl->cmd.state_access); if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST, NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE, 100, TEGRA_SOR_ATTACH_TIMEOUT_MS * 1000)) printk(BIOS_ERR, "dc timeout waiting for OPMOD = AWAKE\n"); else printk(BIOS_INFO, "%s: sor is attached\n", __func__); #if DEBUG_SOR dump_sor_reg(sor); #endif }
static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor, int pu, int is_lvds) { u32 reg_val; /* SOR lane sequencer */ if (pu) reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER | NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU; else reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER | NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP | NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD; if (is_lvds) reg_val |= 15 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT; else reg_val |= 1 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT; tegra_sor_writel(sor, NV_SOR_LANE_SEQ_CTL, reg_val); if (tegra_dc_sor_poll_register(sor, NV_SOR_LANE_SEQ_CTL, NV_SOR_LANE_SEQ_CTL_SETTING_MASK, NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE, 100, TEGRA_SOR_TIMEOUT_MS*1000)) { printk(BIOS_ERR, "dp: timeout while waiting for SOR lane sequencer " "to power down langes\n"); return -1; } return 0; }
static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor, int pu, int is_lvds) { u32 reg_val; /* SOR lane sequencer */ if (pu) { reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER | LANE_SEQ_CTL_SEQUENCE_DOWN | LANE_SEQ_CTL_NEW_POWER_STATE_PU; } else { reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER | LANE_SEQ_CTL_SEQUENCE_UP | LANE_SEQ_CTL_NEW_POWER_STATE_PD; } if (is_lvds) reg_val |= 15 << LANE_SEQ_CTL_DELAY_SHIFT; else reg_val |= 1 << LANE_SEQ_CTL_DELAY_SHIFT; tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val); if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL, LANE_SEQ_CTL_SETTING_MASK, LANE_SEQ_CTL_SETTING_NEW_DONE, 100, TEGRA_SOR_TIMEOUT_MS)) { debug("dp: timeout while waiting for SOR lane sequencer to power down lanes\n"); return -1; } return 0; }
int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd) { u32 reg_val; u32 orig_val; orig_val = tegra_sor_readl(sor, NV_SOR_PWR); reg_val = pu_pd ? NV_SOR_PWR_NORMAL_STATE_PU : NV_SOR_PWR_NORMAL_STATE_PD; /* normal state only */ if (reg_val == orig_val) return 0; /* No update needed */ reg_val |= NV_SOR_PWR_SETTING_NEW_TRIGGER; tegra_sor_writel(sor, NV_SOR_PWR, reg_val); /* Poll to confirm it is done */ if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR, NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK, NV_SOR_PWR_SETTING_NEW_DONE, 100, TEGRA_SOR_TIMEOUT_MS * 1000)) { printk(BIOS_ERR, "dc timeout waiting for SOR_PWR = NEW_DONE\n"); return -EFAULT; } return 0; }
int tegra_dc_sor_set_power_state(struct udevice *dev, int pu_pd) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; u32 orig_val; orig_val = tegra_sor_readl(sor, PWR); reg_val = pu_pd ? PWR_NORMAL_STATE_PU : PWR_NORMAL_STATE_PD; /* normal state only */ if (reg_val == orig_val) return 0; /* No update needed */ reg_val |= PWR_SETTING_NEW_TRIGGER; tegra_sor_writel(sor, PWR, reg_val); /* Poll to confirm it is done */ if (tegra_dc_sor_poll_register(sor, PWR, PWR_SETTING_NEW_DEFAULT_MASK, PWR_SETTING_NEW_DONE, 100, TEGRA_SOR_TIMEOUT_MS)) { debug("dc timeout waiting for SOR_PWR = NEW_DONE\n"); return -EFAULT; } return 0; }
int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); int dc_reg_ctx[DC_REG_SAVE_SPACE]; struct dc_ctlr *disp_ctrl; unsigned long dc_int_mask; int ret; debug("%s\n", __func__); /* Use the first display controller */ disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev); /* Sleep mode */ tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | SUPER_STATE1_ASY_ORMODE_SAFE | SUPER_STATE1_ATTACHED_YES); tegra_dc_sor_super_update(sor); tegra_dc_sor_disable_win_short_raster(disp_ctrl, dc_reg_ctx); if (tegra_dc_sor_poll_register(sor, TEST, TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, TEST_ACT_HEAD_OPMODE_SLEEP, 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) { debug("dc timeout waiting for OPMOD = SLEEP\n"); ret = -ETIMEDOUT; goto err; } tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | SUPER_STATE1_ASY_ORMODE_SAFE | SUPER_STATE1_ATTACHED_NO); /* Mask DC interrupts during the 2 dummy frames required for detach */ dc_int_mask = readl(&disp_ctrl->cmd.int_mask); writel(0, &disp_ctrl->cmd.int_mask); /* Stop DC->SOR path */ tegra_dc_sor_enable_sor(disp_ctrl, false); ret = tegra_dc_sor_general_act(disp_ctrl); if (ret) goto err; /* Stop DC */ writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd); ret = tegra_dc_sor_general_act(disp_ctrl); if (ret) goto err; tegra_dc_sor_restore_win_and_raster(disp_ctrl, dc_reg_ctx); writel(dc_int_mask, &disp_ctrl->cmd.int_mask); return 0; err: debug("%s: ret=%d\n", __func__, ret); return ret; }
void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor) { const struct tegra_dc_dp_link_config *link_cfg = sor->link_cfg; tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL, NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK, NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK); tegra_sor_write_field(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK, NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE); udelay(25); tegra_sor_write_field(sor, NV_SOR_PLL3, NV_SOR_PLL3_PLLVDD_MODE_MASK, NV_SOR_PLL3_PLLVDD_MODE_V3_3); tegra_sor_writel(sor, NV_SOR_PLL0, 0xf << NV_SOR_PLL0_ICHPMP_SHFIT | 0x3 << NV_SOR_PLL0_VCOCAP_SHIFT | NV_SOR_PLL0_PLLREG_LEVEL_V45 | NV_SOR_PLL0_RESISTORSEL_EXT | NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND); tegra_sor_write_field(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX1_SEQ_MASK | NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE | NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE | NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE | NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE); tegra_sor_writel(sor, NV_SOR_PLL1, NV_SOR_PLL1_TERM_COMPOUT_HIGH | NV_SOR_PLL1_TMDS_TERM_ENABLE); if (tegra_dc_sor_poll_register(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE, 100, TEGRA_SOR_TIMEOUT_MS * 1000)) { printk(BIOS_ERR, "DP failed to lock PLL\n"); return; } tegra_sor_write_field(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX2_MASK | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE); tegra_dc_sor_power_up(sor, 0); /* re-enable SOR clock */ tegra_sor_enable_edp_clock(sor); // select pll_dp as clock source /* Power up lanes */ tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1); tegra_dc_sor_set_dp_mode(sor, link_cfg); }
static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div, u32 pwm_dutycycle) { tegra_sor_writel(sor, PWM_DIV, pwm_div); tegra_sor_writel(sor, PWM_CTL, (pwm_dutycycle & PWM_CTL_DUTY_CYCLE_MASK) | PWM_CTL_SETTING_NEW_TRIGGER); if (tegra_dc_sor_poll_register(sor, PWM_CTL, PWM_CTL_SETTING_NEW_SHIFT, PWM_CTL_SETTING_NEW_DONE, 100, TEGRA_SOR_TIMEOUT_MS)) { debug("dp: timeout while waiting for SOR PWM setting\n"); } }
int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev, const struct tegra_dp_link_config *link_cfg, const struct display_timing *timing) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); struct dc_ctlr *disp_ctrl; u32 reg_val; /* Use the first display controller */ debug("%s\n", __func__); disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev); tegra_dc_sor_enable_dc(disp_ctrl); tegra_dc_sor_config_panel(sor, 0, link_cfg, timing); writel(0x9f00, &disp_ctrl->cmd.state_ctrl); writel(0x9f, &disp_ctrl->cmd.state_ctrl); writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, &disp_ctrl->cmd.disp_pow_ctrl); reg_val = tegra_sor_readl(sor, TEST); if (reg_val & TEST_ATTACHED_TRUE) return -EEXIST; tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ATTACHED_NO); /* * Enable display2sor clock at least 2 cycles before DC start, * to clear sor internal valid signal. */ writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); writel(0, &disp_ctrl->disp.disp_win_opt); writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); /* Attach head */ tegra_dc_sor_update(sor); tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ATTACHED_YES); tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ATTACHED_YES | SUPER_STATE1_ASY_HEAD_OP_AWAKE | SUPER_STATE1_ASY_ORMODE_NORMAL); tegra_dc_sor_super_update(sor); /* Enable dc */ reg_val = readl(&disp_ctrl->cmd.state_access); writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd); writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); writel(reg_val, &disp_ctrl->cmd.state_access); if (tegra_dc_sor_poll_register(sor, TEST, TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, TEST_ACT_HEAD_OPMODE_AWAKE, 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) { printf("dc timeout waiting for OPMOD = AWAKE\n"); return -ETIMEDOUT; } else { debug("%s: sor is attached\n", __func__); } #if DEBUG_SOR dump_sor_reg(sor); #endif debug("%s: ret=%d\n", __func__, 0); return 0; }
int tegra_dc_sor_enable_dp(struct udevice *dev, const struct tegra_dp_link_config *link_cfg) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); int ret; tegra_sor_write_field(sor, CLK_CNTRL, CLK_CNTRL_DP_CLK_SEL_MASK, CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK); tegra_sor_write_field(sor, PLL2, PLL2_AUX6_BANDGAP_POWERDOWN_MASK, PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE); udelay(25); tegra_sor_write_field(sor, PLL3, PLL3_PLLVDD_MODE_MASK, PLL3_PLLVDD_MODE_V3_3); tegra_sor_writel(sor, PLL0, 0xf << PLL0_ICHPMP_SHFIT | 0x3 << PLL0_VCOCAP_SHIFT | PLL0_PLLREG_LEVEL_V45 | PLL0_RESISTORSEL_EXT | PLL0_PWR_ON | PLL0_VCOPD_RESCIND); tegra_sor_write_field(sor, PLL2, PLL2_AUX1_SEQ_MASK | PLL2_AUX9_LVDSEN_OVERRIDE | PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE | PLL2_AUX9_LVDSEN_OVERRIDE | PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE); tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | PLL1_TMDS_TERM_ENABLE); if (tegra_dc_sor_poll_register(sor, PLL2, PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE, 100, TEGRA_SOR_TIMEOUT_MS)) { printf("DP failed to lock PLL\n"); return -EIO; } tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK | PLL2_AUX7_PORT_POWERDOWN_MASK, PLL2_AUX2_OVERRIDE_POWERDOWN | PLL2_AUX7_PORT_POWERDOWN_DISABLE); ret = tegra_dc_sor_power_up(dev, 0); if (ret) { debug("DP failed to power up\n"); return ret; } /* re-enable SOR clock */ clock_sor_enable_edp_clock(); /* Power up lanes */ tegra_dc_sor_power_dplanes(dev, link_cfg->lane_count, 1); tegra_dc_sor_set_dp_mode(dev, link_cfg); debug("%s ret\n", __func__); return 0; }