static void tegra_camera_init(void)
{
/* For AP37 platform, limit 3d and emc freq when camera is ON */
if (TEGRA_REVISION_A03 == tegra_get_revision() &&
0xA0 == tegra_sku_id())
tegra_camera_pdata.limit_3d_emc_clk = true;
else
tegra_camera_pdata.limit_3d_emc_clk = false;
}
void tegra_init_fuse(void)
{
u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
reg |= 1 << 28;
writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
tegra_init_speedo_data();
pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
tegra_revision_name[tegra_get_revision()],
tegra_sku_id(), tegra_cpu_process_id(),
tegra_core_process_id());
}
void __init tegra3_init_timer(u32 *offset, int *irq)
{
unsigned long rate = tegra_clk_measure_input_freq();
switch (rate) {
case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG);
break;
case 13000000:
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
case 19200000:
timer_writel(0x045f, TIMERUS_USEC_CFG);
break;
case 26000000:
timer_writel(0x0019, TIMERUS_USEC_CFG);
break;
case 16800000:
timer_writel(0x0453, TIMERUS_USEC_CFG);
break;
case 38400000:
timer_writel(0x04BF, TIMERUS_USEC_CFG);
break;
case 48000000:
timer_writel(0x002F, TIMERUS_USEC_CFG);
break;
default:
WARN(1, "Unknown clock rate");
}
#ifdef CONFIG_PM_SLEEP
#ifdef CONFIG_SMP
/* For T30.A01 use INT_TMR_SHARED instead of INT_TMR6 for CPU3. */
if ((tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) &&
(tegra_get_revision() == TEGRA_REVISION_A01))
tegra_lp2wake_irq[3].irq = INT_TMR_SHARED;
#endif
tegra3_register_wake_timer(0);
#endif
*offset = TIMER1_OFFSET;
*irq = INT_TMR1;
}
int __init enterprise_panel_init(void)
{
int err;
struct resource __maybe_unused *res;
bl_output = enterprise_bl_output_measured;
if (WARN_ON(ARRAY_SIZE(enterprise_bl_output_measured) != 256))
pr_err("bl_output array does not have 256 elements\n");
enterprise_dsi.chip_id = tegra_get_chipid();
enterprise_dsi.chip_rev = tegra_get_revision();
enterprise_carveouts[1].base = tegra_carveout_start;
enterprise_carveouts[1].size = tegra_carveout_size;
tegra_gpio_enable(enterprise_hdmi_hpd);
gpio_request(enterprise_hdmi_hpd, "hdmi_hpd");
gpio_direction_input(enterprise_hdmi_hpd);
tegra_gpio_enable(enterprise_lcd_2d_3d);
gpio_request(enterprise_lcd_2d_3d, "lcd_2d_3d");
gpio_direction_output(enterprise_lcd_2d_3d, 0);
enterprise_stereo_set_mode(enterprise_stereo.mode_2d_3d);
tegra_gpio_enable(enterprise_lcd_swp_pl);
gpio_request(enterprise_lcd_swp_pl, "lcd_swp_pl");
gpio_direction_output(enterprise_lcd_swp_pl, 0);
enterprise_stereo_set_orientation(enterprise_stereo.orientation);
#if !(DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
tegra_gpio_enable(enterprise_lcd_te);
gpio_request(enterprise_lcd_swp_pl, "lcd_te");
gpio_direction_input(enterprise_lcd_te);
#endif
#ifdef CONFIG_HAS_EARLYSUSPEND
enterprise_panel_early_suspender.suspend = enterprise_panel_early_suspend;
enterprise_panel_early_suspender.resume = enterprise_panel_late_resume;
enterprise_panel_early_suspender.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
register_early_suspend(&enterprise_panel_early_suspender);
#endif
err = platform_add_devices(enterprise_gfx_devices,
ARRAY_SIZE(enterprise_gfx_devices));
#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
res = nvhost_get_resource_byname(&enterprise_disp1_device,
IORESOURCE_MEM, "fbmem");
res->start = tegra_fb_start;
res->end = tegra_fb_start + tegra_fb_size - 1;
#endif
/* Copy the bootloader fb to the fb. */
tegra_move_framebuffer(tegra_fb_start, tegra_bootloader_fb_start,
min(tegra_fb_size, tegra_bootloader_fb_size));
#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
if (!err)
err = nvhost_device_register(&enterprise_disp1_device);
res = nvhost_get_resource_byname(&enterprise_disp2_device,
IORESOURCE_MEM, "fbmem");
res->start = tegra_fb2_start;
res->end = tegra_fb2_start + tegra_fb2_size - 1;
if (!err)
err = nvhost_device_register(&enterprise_disp2_device);
#endif
#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP)
if (!err)
err = nvhost_device_register(&nvavp_device);
#endif
if (!err)
err = platform_add_devices(enterprise_bl_devices,
ARRAY_SIZE(enterprise_bl_devices));
return err;
}
void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
unsigned long fb2_size)
{
#ifdef SUPPORT_SMMU_BASE_FOR_TEGRA3_A01
int smmu_reserved = 0;
struct tegra_smmu_window *smmu_window = tegra_smmu_window(0);
#endif
if (carveout_size) {
tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
if (memblock_remove(tegra_carveout_start, carveout_size)) {
pr_err("Failed to remove carveout %08lx@%08lx "
"from memory map\n",
carveout_size, tegra_carveout_start);
tegra_carveout_start = 0;
tegra_carveout_size = 0;
} else
tegra_carveout_size = carveout_size;
}
if (fb2_size) {
tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
if (memblock_remove(tegra_fb2_start, fb2_size)) {
pr_err("Failed to remove second framebuffer "
"%08lx@%08lx from memory map\n",
fb2_size, tegra_fb2_start);
tegra_fb2_start = 0;
tegra_fb2_size = 0;
} else
tegra_fb2_size = fb2_size;
}
if (fb_size) {
tegra_fb_start = memblock_end_of_DRAM() - fb_size;
if (memblock_remove(tegra_fb_start, fb_size)) {
pr_err("Failed to remove framebuffer %08lx@%08lx "
"from memory map\n",
fb_size, tegra_fb_start);
tegra_fb_start = 0;
tegra_fb_size = 0;
} else
tegra_fb_size = fb_size;
}
if (tegra_fb_size)
tegra_grhost_aperture = tegra_fb_start;
if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
tegra_grhost_aperture = tegra_fb2_start;
if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
tegra_grhost_aperture = tegra_carveout_start;
#ifdef SUPPORT_SMMU_BASE_FOR_TEGRA3_A01
if (!smmu_window) {
pr_err("No SMMU resource\n");
} else {
size_t smmu_window_size;
if (FORCE_SMMU_BASE_FOR_TEGRA3_A01 ||
(tegra_get_chipid() == TEGRA_CHIPID_TEGRA3 &&
tegra_get_revision() == TEGRA_REVISION_A01)) {
smmu_window->start = TEGRA_SMMU_BASE_TEGRA3_A01;
smmu_window->end = TEGRA_SMMU_BASE_TEGRA3_A01 +
TEGRA_SMMU_SIZE_TEGRA3_A01 - 1;
}
smmu_window_size = smmu_window->end + 1 - smmu_window->start;
if (smmu_window->start >= 0x80000000) {
if (memblock_reserve(smmu_window->start,
smmu_window_size))
pr_err(
"Failed to reserve SMMU I/O VA window %08lx@%08lx\n",
(unsigned long)smmu_window_size,
(unsigned long)smmu_window->start);
else
smmu_reserved = 1;
}
}
#endif
if (tegra_lp0_vec_size &&
(tegra_lp0_vec_start < memblock_end_of_DRAM())) {
if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
tegra_lp0_vec_size, tegra_lp0_vec_start);
tegra_lp0_vec_start = 0;
tegra_lp0_vec_size = 0;
}
tegra_lp0_vec_relocate = false;
} else
tegra_lp0_vec_relocate = true;
/*
* We copy the bootloader's framebuffer to the framebuffer allocated
* above, and then free this one.
* */
if (tegra_bootloader_fb_size) {
tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
if (memblock_reserve(tegra_bootloader_fb_start,
tegra_bootloader_fb_size)) {
pr_err("Failed to reserve bootloader frame buffer "
"%08lx@%08lx\n", tegra_bootloader_fb_size,
tegra_bootloader_fb_start);
tegra_bootloader_fb_start = 0;
tegra_bootloader_fb_size = 0;
}
}
pr_info("Tegra reserved memory:\n"
"LP0: %08lx - %08lx\n"
"Bootloader framebuffer: %08lx - %08lx\n"
"Framebuffer: %08lx - %08lx\n"
"2nd Framebuffer: %08lx - %08lx\n"
"Carveout: %08lx - %08lx\n"
"Vpr: %08lx - %08lx\n",
tegra_lp0_vec_start,
tegra_lp0_vec_size ?
tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
tegra_bootloader_fb_start,
tegra_bootloader_fb_size ?
tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
tegra_fb_start,
tegra_fb_size ?
tegra_fb_start + tegra_fb_size - 1 : 0,
tegra_fb2_start,
tegra_fb2_size ?
tegra_fb2_start + tegra_fb2_size - 1 : 0,
tegra_carveout_start,
tegra_carveout_size ?
tegra_carveout_start + tegra_carveout_size - 1 : 0,
tegra_vpr_start,
tegra_vpr_size ?
tegra_vpr_start + tegra_vpr_size - 1 : 0);
#ifdef SUPPORT_SMMU_BASE_FOR_TEGRA3_A01
if (smmu_reserved)
pr_info("SMMU: %08lx - %08lx\n",
smmu_window->start, smmu_window->end);
#endif
}
