SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
{
SH7750State *s;
s = g_malloc0(sizeof(SH7750State));
s->cpu = cpu;
s->periph_freq = 60000000; /* 60MHz */
memory_region_init_io(&s->iomem, &sh7750_mem_ops, s,
"memory", 0x1fc01000);
memory_region_init_alias(&s->iomem_1f0, "memory-1f0",
&s->iomem, 0x1f000000, 0x1000);
memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0);
memory_region_init_alias(&s->iomem_ff0, "memory-ff0",
&s->iomem, 0x1f000000, 0x1000);
memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0);
memory_region_init_alias(&s->iomem_1f8, "memory-1f8",
&s->iomem, 0x1f800000, 0x1000);
memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8);
memory_region_init_alias(&s->iomem_ff8, "memory-ff8",
&s->iomem, 0x1f800000, 0x1000);
memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8);
memory_region_init_alias(&s->iomem_1fc, "memory-1fc",
&s->iomem, 0x1fc00000, 0x1000);
memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc);
memory_region_init_alias(&s->iomem_ffc, "memory-ffc",
&s->iomem, 0x1fc00000, 0x1000);
memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc);
memory_region_init_io(&s->mmct_iomem, &sh7750_mmct_ops, s,
"cache-and-tlb", 0x08000000);
memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
sh_intc_init(sysmem, &s->intc, NR_SOURCES,
_INTC_ARRAY(mask_registers),
_INTC_ARRAY(prio_registers));
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors),
_INTC_ARRAY(groups));
cpu->intc_handle = &s->intc;
sh_serial_init(sysmem, 0x1fe00000,
0, s->periph_freq, serial_hds[0],
s->intc.irqs[SCI1_ERI],
s->intc.irqs[SCI1_RXI],
s->intc.irqs[SCI1_TXI],
s->intc.irqs[SCI1_TEI],
NULL);
sh_serial_init(sysmem, 0x1fe80000,
SH_SERIAL_FEAT_SCIF,
s->periph_freq, serial_hds[1],
s->intc.irqs[SCIF_ERI],
s->intc.irqs[SCIF_RXI],
s->intc.irqs[SCIF_TXI],
NULL,
s->intc.irqs[SCIF_BRI]);
tmu012_init(sysmem, 0x1fd80000,
TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
s->periph_freq,
s->intc.irqs[TMU0],
s->intc.irqs[TMU1],
s->intc.irqs[TMU2_TUNI],
s->intc.irqs[TMU2_TICPI]);
if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_dma4),
_INTC_ARRAY(groups_dma4));
}
if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_dma8),
_INTC_ARRAY(groups_dma8));
}
if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_tmu34),
NULL, 0);
tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq,
s->intc.irqs[TMU3],
s->intc.irqs[TMU4],
NULL, NULL);
}
if (cpu->id & (SH_CPU_SH7751_ALL)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_pci),
_INTC_ARRAY(groups_pci));
}
if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_irlm),
NULL, 0);
}
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_irl),
_INTC_ARRAY(groups_irl));
return s;
}
SH7750State *sh7750_init(CPUSH4State * cpu)
{
SH7750State *s;
int sh7750_io_memory;
int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
s = qemu_mallocz(sizeof(SH7750State));
s->cpu = cpu;
s->periph_freq = 60000000; /* 60MHz */
sh7750_io_memory = cpu_register_io_memory(0,
sh7750_mem_read,
sh7750_mem_write, s);
cpu_register_physical_memory_offset(0x1f000000, 0x1000,
sh7750_io_memory, 0x1f000000);
cpu_register_physical_memory_offset(0xff000000, 0x1000,
sh7750_io_memory, 0x1f000000);
cpu_register_physical_memory_offset(0x1f800000, 0x1000,
sh7750_io_memory, 0x1f800000);
cpu_register_physical_memory_offset(0xff800000, 0x1000,
sh7750_io_memory, 0x1f800000);
cpu_register_physical_memory_offset(0x1fc00000, 0x1000,
sh7750_io_memory, 0x1fc00000);
cpu_register_physical_memory_offset(0xffc00000, 0x1000,
sh7750_io_memory, 0x1fc00000);
sh7750_mm_cache_and_tlb = cpu_register_io_memory(0,
sh7750_mmct_read,
sh7750_mmct_write, s);
cpu_register_physical_memory(0xf0000000, 0x08000000,
sh7750_mm_cache_and_tlb);
sh_intc_init(&s->intc, NR_SOURCES,
_INTC_ARRAY(mask_registers),
_INTC_ARRAY(prio_registers));
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors),
_INTC_ARRAY(groups));
cpu->intc_handle = &s->intc;
sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0],
s->intc.irqs[SCI1_ERI],
s->intc.irqs[SCI1_RXI],
s->intc.irqs[SCI1_TXI],
s->intc.irqs[SCI1_TEI],
NULL);
sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
s->periph_freq, serial_hds[1],
s->intc.irqs[SCIF_ERI],
s->intc.irqs[SCIF_RXI],
s->intc.irqs[SCIF_TXI],
NULL,
s->intc.irqs[SCIF_BRI]);
tmu012_init(0x1fd80000,
TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
s->periph_freq,
s->intc.irqs[TMU0],
s->intc.irqs[TMU1],
s->intc.irqs[TMU2_TUNI],
s->intc.irqs[TMU2_TICPI]);
if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_dma4),
_INTC_ARRAY(groups_dma4));
}
if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_dma8),
_INTC_ARRAY(groups_dma8));
}
if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_tmu34),
NULL, 0);
tmu012_init(0x1e100000, 0, s->periph_freq,
s->intc.irqs[TMU3],
s->intc.irqs[TMU4],
NULL, NULL);
}
if (cpu->id & (SH_CPU_SH7751_ALL)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_pci),
_INTC_ARRAY(groups_pci));
}
if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_irlm),
NULL, 0);
}
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_irl),
_INTC_ARRAY(groups_irl));
return s;
}
