int timer_init (void)
{
/* Divide clock by TMU_CLK_DIVIDER */
u16 bit = 0;
switch (TMU_CLK_DIVIDER) {
case 1024:
bit = 4;
break;
case 256:
bit = 3;
break;
case 64:
bit = 2;
break;
case 16:
bit = 1;
break;
case 4:
default:
break;
}
writew(readw(TCR0) | bit, TCR0);
/* Clock frequency calc */
timer_freq = get_tmu0_clk_rate() >> ((bit + 1) * 2);
tmu_timer_stop(0);
tmu_timer_start(0);
return 0;
}
int timer_init (void)
{
/* Divide clock by CONFIG_SYS_TMU_CLK_DIV */
u16 bit = 0;
switch (CONFIG_SYS_TMU_CLK_DIV) {
case 1024:
bit = 4;
break;
case 256:
bit = 3;
break;
case 64:
bit = 2;
break;
case 16:
bit = 1;
break;
case 4:
default:
break;
}
writew(readw(TCR0) | bit, TCR0);
/* Calc clock rate */
timer_freq = get_tmu0_clk_rate() >> ((bit + 1) * 2);
tmu_timer_stop(0);
tmu_timer_start(0);
last_tcnt = 0;
overflow_ticks = 0;
return 0;
}
void set_timer (unsigned long t)
{
/* Note: timer must be STOPPED to update it */
tmu_timer_stop(0);
writel((0 - t), TCNT0);
tmu_timer_start(0);
}
int timer_init (void)
{
/* Divide clock by 4 */
*(volatile u16 *)TCR0 = 0;
tmu_timer_stop(0);
tmu_timer_start(0);
return 0;
}
int timer_init(void)
{
/* Divide clock by 4 */
outw(0, TCR0);
tmu_timer_stop(0);
tmu_timer_start(0);
return 0;
}
static void tmu0_timer_set_interval(unsigned long interval, unsigned int reload)
{
ctrl_outl(interval, TMU0_TCNT);
/*
* TCNT reloads from TCOR on underflow, clear it if we don't
* intend to auto-reload
*/
if (reload)
ctrl_outl(interval, TMU0_TCOR);
else
ctrl_outl(0, TMU0_TCOR);
tmu_timer_start();
}
void reset_timer (void)
{
tmu_timer_stop(0);
set_timer (0);
tmu_timer_start(0);
}
