static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset, enum GPIO_REG reg_type) { struct lnw_gpio *lnw = to_lnw_priv(chip); unsigned nreg = chip->ngpio / 32; u8 reg = offset / 16; void __iomem *ptr; ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4); return ptr; }
static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, enum GPIO_REG reg_type) { struct lnw_gpio *lnw = to_lnw_priv(chip); unsigned nreg = chip->ngpio / 32; u8 reg = offset / 32; void __iomem *ptr; void *base; /** * On TNG B0, GITR[0]'s address is 0xFF008300, while GPLR[0]'s address * is 0xFF008004. To count GITR[0]'s address, it's easier to count * from 0xFF008000. So for GITR,GLPR... we switch the base to reg_base. * This does not affect PNW/CLV, since the reg_gplr is the reg_base, * while on TNG, the reg_gplr has an offset of 0x4. */ base = reg_type < GITR ? lnw->reg_gplr : lnw->reg_base; ptr = (void __iomem *)(base + reg_type * nreg * 4 + reg * 4); return ptr; }
static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { struct lnw_gpio *lnw = to_lnw_priv(chip); void __iomem *gpdr = gpio_reg(chip, offset, GPDR); u32 value; unsigned long flags; if (lnw->pdev) pm_runtime_get(&lnw->pdev->dev); spin_lock_irqsave(&lnw->lock, flags); value = readl(gpdr); value &= ~BIT(offset % 32); writel(value, gpdr); spin_unlock_irqrestore(&lnw->lock, flags); if (lnw->pdev) pm_runtime_put(&lnw->pdev->dev); return 0; }
static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset) { struct lnw_gpio *lnw = to_lnw_priv(chip); return irq_create_mapping(lnw->domain, offset); }