コード例 #1
0
ファイル: mvgbe.c プロジェクト: Grommerin/u-boot-bars3000
static int mvgbe_halt(struct eth_device *dev)
{
    struct mvgbe_device *dmvgbe = to_mvgbe(dev);
    struct mvgbe_registers *regs = dmvgbe->regs;

    /* Disable all gigE address decoder */
    MVGBE_REG_WR(regs->bare, 0x3f);

    stop_queue(&regs->tqc);
    stop_queue(&regs->rqc);

    /* Disable port */
    MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
    /* Set port is not reset */
    MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
#ifdef CONFIG_SYS_MII_MODE
    /* Set MMI interface up */
    MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
#endif
    /* Disable & mask ethernet port interrupts */
    MVGBE_REG_WR(regs->ic, 0);
    MVGBE_REG_WR(regs->ice, 0);
    MVGBE_REG_WR(regs->pim, 0);
    MVGBE_REG_WR(regs->peim, 0);

    return 0;
}
コード例 #2
0
ファイル: mvgbe.c プロジェクト: Grommerin/u-boot-bars3000
static int mvgbe_write_hwaddr(struct eth_device *dev)
{
    struct mvgbe_device *dmvgbe = to_mvgbe(dev);
    struct mvgbe_registers *regs = dmvgbe->regs;

    /* Programs net device MAC address after initialization */
    port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
    return 0;
}
コード例 #3
0
ファイル: mvgbe.c プロジェクト: Apaisal/u-boot
static int mvgbe_send(struct eth_device *dev, void *dataptr,
		      int datasize)
{
	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
	struct mvgbe_registers *regs = dmvgbe->regs;
	struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
	void *p = (void *)dataptr;
	u32 cmd_sts;
	u32 txuq0_reg_addr;

	/* Copy buffer if it's misaligned */
	if ((u32) dataptr & 0x07) {
		if (datasize > PKTSIZE_ALIGN) {
			printf("Non-aligned data too large (%d)\n",
					datasize);
			return -1;
		}

		memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
		p = dmvgbe->p_aligned_txbuf;
	}

	p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
	p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
	p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
	p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
	p_txdesc->buf_ptr = (u8 *) p;
	p_txdesc->byte_cnt = datasize;

	/* Set this tc desc as zeroth TXUQ */
	txuq0_reg_addr = (u32)&regs->tcqdp[TXUQ];
	writel((u32) p_txdesc, txuq0_reg_addr);

	/* ensure tx desc writes above are performed before we start Tx DMA */
	isb();

	/* Apply send command using zeroth TXUQ */
	MVGBE_REG_WR(regs->tqc, (1 << TXUQ));

	/*
	 * wait for packet xmit completion
	 */
	cmd_sts = readl(&p_txdesc->cmd_sts);
	while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
		/* return fail if error is detected */
		if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
				(MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
				cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
			printf("Err..(%s) in xmit packet\n", __FUNCTION__);
			return -1;
		}
		cmd_sts = readl(&p_txdesc->cmd_sts);
	};
	return 0;
}
コード例 #4
0
ファイル: mvgbe.c プロジェクト: Grommerin/u-boot-bars3000
/*
 * smi_reg_write - imiiphy_write callback function.
 *
 * Returns 0 if write succeed, -EINVAL on bad parameters
 * -ETIME on timeout
 */
static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
{
    struct eth_device *dev = eth_get_dev_by_name(devname);
    struct mvgbe_device *dmvgbe = to_mvgbe(dev);
    struct mvgbe_registers *regs = dmvgbe->regs;
    u32 smi_reg;
    u32 timeout;

    /* Phyadr write request*/
    if (phy_adr == MV_PHY_ADR_REQUEST &&
            reg_ofs == MV_PHY_ADR_REQUEST) {
        MVGBE_REG_WR(regs->phyadr, data);
        return 0;
    }

    /* check parameters */
    if (phy_adr > PHYADR_MASK) {
        printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
        return -EINVAL;
    }
    if (reg_ofs > PHYREG_MASK) {
        printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
        return -EINVAL;
    }

    /* wait till the SMI is not busy */
    timeout = MVGBE_PHY_SMI_TIMEOUT;
    do {
        /* read smi register */
        smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
        if (timeout-- == 0) {
            printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
            return -ETIME;
        }
    } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);

    /* fill the phy addr and reg offset and write opcode and data */
    smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
    smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
               | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
    smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;

    /* write the smi register */
    MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);

    return 0;
}
コード例 #5
0
ファイル: mvgbe.c プロジェクト: Grommerin/u-boot-bars3000
/*
 * smi_reg_read - miiphy_read callback function.
 *
 * Returns 16bit phy register value, or 0xffff on error
 */
static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
{
    struct eth_device *dev = eth_get_dev_by_name(devname);
    struct mvgbe_device *dmvgbe = to_mvgbe(dev);
    struct mvgbe_registers *regs = dmvgbe->regs;
    u32 smi_reg;
    u32 timeout;

    /* Phyadr read request */
    if (phy_adr == MV_PHY_ADR_REQUEST &&
            reg_ofs == MV_PHY_ADR_REQUEST) {
        /* */
        *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
        return 0;
    }
    /* check parameters */
    if (phy_adr > PHYADR_MASK) {
        printf("Err..(%s) Invalid PHY address %d\n",
               __FUNCTION__, phy_adr);
        return -EFAULT;
    }
    if (reg_ofs > PHYREG_MASK) {
        printf("Err..(%s) Invalid register offset %d\n",
               __FUNCTION__, reg_ofs);
        return -EFAULT;
    }

    timeout = MVGBE_PHY_SMI_TIMEOUT;
    /* wait till the SMI is not busy */
    do {
        /* read smi register */
        smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
        if (timeout-- == 0) {
            printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
            return -EFAULT;
        }
    } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);

    /* fill the phy address and regiser offset and read opcode */
    smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
              | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
              | MVGBE_PHY_SMI_OPCODE_READ;

    /* write the smi register */
    MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);

    /*wait till read value is ready */
    timeout = MVGBE_PHY_SMI_TIMEOUT;

    do {
        /* read smi register */
        smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
        if (timeout-- == 0) {
            printf("Err..(%s) SMI read ready timeout\n",
                   __FUNCTION__);
            return -EFAULT;
        }
    } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));

    /* Wait for the data to update in the SMI register */
    for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
        ;

    *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);

    debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
          reg_ofs, *data);

    return 0;
}
コード例 #6
0
ファイル: mvgbe.c プロジェクト: Grommerin/u-boot-bars3000
static int mvgbe_recv(struct eth_device *dev)
{
    struct mvgbe_device *dmvgbe = to_mvgbe(dev);
    struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
    u32 cmd_sts;
    u32 timeout = 0;

    /* wait untill rx packet available or timeout */
    do {
        if (timeout < MVGBE_PHY_SMI_TIMEOUT)
            timeout++;
        else {
            debug("%s time out...\n", __FUNCTION__);
            return -1;
        }
    } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);

    if (p_rxdesc_curr->byte_cnt != 0) {
        debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
              __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
              (u32) p_rxdesc_curr->buf_ptr,
              (u32) p_rxdesc_curr->cmd_sts);
    }

    /*
     * In case received a packet without first/last bits on
     * OR the error summary bit is on,
     * the packets needs to be dropeed.
     */
    cmd_sts = readl(&p_rxdesc_curr->cmd_sts);

    if ((cmd_sts &
            (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
            != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {

        printf("Err..(%s) Dropping packet spread on"
               " multiple descriptors\n", __FUNCTION__);

    } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {

        printf("Err..(%s) Dropping packet with errors\n",
               __FUNCTION__);

    } else {
        /* !!! call higher layer processing */
        debug("%s: Sending Received packet to"
              " upper layer (NetReceive)\n", __FUNCTION__);

        /* let the upper layer handle the packet */
        NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
                   (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
    }
    /*
     * free these descriptors and point next in the ring
     */
    p_rxdesc_curr->cmd_sts =
        MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
    p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
    p_rxdesc_curr->byte_cnt = 0;

    writel((unsigned)p_rxdesc_curr->nxtdesc_p,
           (u32) &dmvgbe->p_rxdesc_curr);

    return 0;
}
コード例 #7
0
ファイル: mvgbe.c プロジェクト: Grommerin/u-boot-bars3000
static int mvgbe_init(struct eth_device *dev)
{
    struct mvgbe_device *dmvgbe = to_mvgbe(dev);
    struct mvgbe_registers *regs = dmvgbe->regs;
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
    int i;
#endif
    /* setup RX rings */
    mvgbe_init_rx_desc_ring(dmvgbe);

    /* Clear the ethernet port interrupts */
    MVGBE_REG_WR(regs->ic, 0);
    MVGBE_REG_WR(regs->ice, 0);
    /* Unmask RX buffer and TX end interrupt */
    MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
    /* Unmask phy and link status changes interrupts */
    MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);

    set_dram_access(regs);
    port_init_mac_tables(regs);
    port_uc_addr_set(regs, dmvgbe->dev.enetaddr);

    /* Assign port configuration and command. */
    MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
    MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
    MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);

    /* Assign port SDMA configuration */
    MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
    MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
    MVGBE_REG_WR(regs->tqx[0].tqxtbc,
                 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
    /* Turn off the port/RXUQ bandwidth limitation */
    MVGBE_REG_WR(regs->pmtu, 0);

    /* Set maximum receive buffer to 9700 bytes */
    MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
                 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));

    /* Enable port initially */
    MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);

    /*
     * Set ethernet MTU for leaky bucket mechanism to 0 - this will
     * disable the leaky bucket mechanism .
     */
    MVGBE_REG_WR(regs->pmtu, 0);

    /* Assignment of Rx CRDB of given RXUQ */
    MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
    /* ensure previous write is done before enabling Rx DMA */
    isb();
    /* Enable port Rx. */
    MVGBE_REG_WR(regs->rqc, (1 << RXUQ));

#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
    /* Wait up to 5s for the link status */
    for (i = 0; i < 5; i++) {
        u16 phyadr;

        miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
                    MV_PHY_ADR_REQUEST, &phyadr);
        /* Return if we get link up */
        if (miiphy_link(dev->name, phyadr))
            return 0;
        udelay(1000000);
    }

    printf("No link on %s\n", dev->name);
    return -1;
#endif
    return 0;
}