static unsigned long adv7180_query_bus_param(struct soc_camera_device *icd)
{
struct soc_camera_link *icl = to_soc_camera_link(icd);
unsigned long flags = SENSOR_BUS_PARAM;
return soc_camera_apply_sensor_flags(icl, flags);
}
/* Request bus settings on camera side */
static unsigned long gc0329_query_bus_param(struct soc_camera_device *icd)
{
struct soc_camera_link *icl = to_soc_camera_link(icd);
unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER |
SOCAM_VSYNC_ACTIVE_LOW | SOCAM_HSYNC_ACTIVE_HIGH |
SOCAM_DATA_ACTIVE_HIGH | SOCAM_DATAWIDTH_8;
return soc_camera_apply_sensor_flags(icl, flags);
}
/* Request bus settings on camera side */
static unsigned long gc0309_query_bus_param(struct soc_camera_device *icd)
{
struct soc_camera_link *icl = to_soc_camera_link(icd);
struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
cfg.flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
V4L2_MBUS_VSYNC_ACTIVE_LOW | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
V4L2_MBUS_DATA_ACTIVE_HIGH;
return soc_camera_apply_board_flags(icl, &cfg);
}
static void adv7180_pwr_ctl(struct soc_camera_device *icd, bool onoff)
{
struct soc_camera_link *icl = to_soc_camera_link(icd);
int enable;
if(onoff == 0)
enable = 1;
else
enable = 0;
if (icl->powerdown) {
icl->powerdown(icd->pdev, enable);
msleep(10);
}
}
/*
* i2c_driver function
*/
static int gc0329_probe(struct i2c_client *client,
const struct i2c_device_id *did)
{
struct gc0329_priv *priv;
struct soc_camera_device *icd = client->dev.platform_data;
struct soc_camera_link *icl;
int ret;
if (!icd) {
dev_err(&client->dev, "Missing soc-camera data!\n");
return -EINVAL;
}
icl = to_soc_camera_link(icd);
if (!icl) {
dev_err(&client->dev, "Missing platform_data for driver\n");
return -EINVAL;
}
priv = kzalloc(sizeof(struct gc0329_priv), GFP_KERNEL);
if (!priv) {
dev_err(&client->dev, "Failed to allocate private data!\n");
return -ENOMEM;
}
v4l2_i2c_subdev_init(&priv->subdev, client, &gc0329_subdev_ops);
icd->ops = &gc0329_ops;
ret = gc0329_video_probe(icd, client);
if (ret < 0) {
goto err_probe;
}
#ifdef DEBUG_EN
sysfs_create_group(&client->dev.kobj, &dev_attr_group);
#endif
return 0;
err_probe:
icd->ops = NULL;
kfree(priv);
return ret;
}
static int hawaii_camera_power_front(struct device *dev, int on)
{
unsigned int value;
int ret = -1;
struct clk *clock;
struct clk *axi_clk;
struct clk *axi_clk_0;
struct clk *lp_clock_0;
struct clk *lp_clock_1;
static struct pi_mgr_dfs_node unicam_dfs_node;
struct soc_camera_device *icd = to_soc_camera_dev(dev);
struct soc_camera_link *icl = to_soc_camera_link(icd);
printk(KERN_INFO "%s:camera power %s\n", __func__, (on ? "on" : "off"));
struct cameraCfg_s *thisCfg = getCameraCfg(icl->module_name);
if (NULL == thisCfg) {
printk(KERN_ERR "No cfg for [%s]\n", icl->module_name);
return -1;
}
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
return -1;
}
if (gpio_request_one(SENSOR_1_GPIO_PWRDN, GPIOF_DIR_OUT |
(thisCfg->pwdn_active<<1), "Cam1PWDN")) {
printk(KERN_ERR "Unable to get CAM1PWDN\n");
return -1;
}
if (gpio_request_one(SENSOR_1_GPIO_RST, GPIOF_DIR_OUT |
(thisCfg->rst_active<<1), "Cam1RST")) {
printk(KERN_ERR "Unable to get Cam1RST\n");
return -1;
}
d_lvldo2_cam1_1v8 = regulator_get(NULL,
icl->regulators[0].supply);
if (IS_ERR_OR_NULL(d_lvldo2_cam1_1v8))
printk(KERN_ERR "Failed to get d_lvldo2_cam1_1v8\n");
if (d_1v8_mmc1_vcc == NULL) {
d_1v8_mmc1_vcc = regulator_get(NULL,
icl->regulators[1].supply);
if (IS_ERR_OR_NULL(d_1v8_mmc1_vcc))
printk(KERN_ERR "Err d_1v8_mmc1_vcc\n");
}
if (d_3v0_mmc1_vcc == NULL) {
d_3v0_mmc1_vcc = regulator_get(NULL,
icl->regulators[2].supply);
if (IS_ERR_OR_NULL(d_3v0_mmc1_vcc))
printk(KERN_ERR "d_3v0_mmc1_vcc");
}
if (d_gpsr_cam0_1v8 == NULL) {
d_gpsr_cam0_1v8 = regulator_get(NULL,
icl->regulators[3].supply);
if (IS_ERR_OR_NULL(d_gpsr_cam0_1v8))
printk(KERN_ERR "Fl d_gpsr_cam0_1v8 get fail");
}
}
ret = -1;
lp_clock_0 = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock_0)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI0_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
lp_clock_1 = clk_get(NULL, CSI1_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock_1)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI1_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
clock = clk_get(NULL, SENSOR_1_CLK);
if (IS_ERR_OR_NULL(clock)) {
printk(KERN_ERR "Unable to get SENSOR_1 clock\n");
goto e_clk_get;
}
axi_clk_0 = clk_get(NULL, "csi0_axi_clk");
if (IS_ERR_OR_NULL(axi_clk_0)) {
printk(KERN_ERR "Unable to get AXI clock 0\n");
goto e_clk_get;
}
axi_clk = clk_get(NULL, "csi1_axi_clk");
if (IS_ERR_OR_NULL(axi_clk)) {
printk(KERN_ERR "Unable to get AXI clock 1\n");
goto e_clk_get;
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO))
printk("DVFS for UNICAM failed\n");
gpio_set_value(SENSOR_1_GPIO_PWRDN, thisCfg->pwdn_active);
gpio_set_value(SENSOR_1_GPIO_RST, thisCfg->rst_active);
usleep_range(5000, 5010);
regulator_enable(d_lvldo2_cam1_1v8);
usleep_range(1000, 1010);
regulator_enable(d_1v8_mmc1_vcc);
usleep_range(1000, 1010);
/* Secondary cam addition */
regulator_enable(d_gpsr_cam0_1v8);
usleep_range(1000, 1010);
regulator_enable(d_3v0_mmc1_vcc);
usleep_range(1000, 1010);
gpio_set_value(SENSOR_1_GPIO_RST,
thisCfg->rst_active ? 0 : 1);
if (mm_ccu_set_pll_select(CSI1_BYTE1_PLL, 8)) {
pr_err("failed to set BYTE1\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI1_BYTE0_PLL, 8)) {
pr_err("failed to set BYTE0\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI1_CAMPIX_PLL, 8)) {
pr_err("failed to set PIXPLL\n");
goto e_clk_pll;
}
value = clk_enable(lp_clock_0);
if (value) {
printk(KERN_ERR "Failed to enable lp clock 0\n");
goto e_clk_lp0;
}
value = clk_set_rate(lp_clock_0, CSI0_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock 0\n");
goto e_clk_set_lp0;
}
value = clk_enable(lp_clock_1);
if (value) {
pr_err(KERN_ERR "Failed to enable lp clock 1\n");
goto e_clk_lp1;
}
value = clk_set_rate(lp_clock_1, CSI1_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock 1\n");
goto e_clk_set_lp1;
}
value = clk_enable(axi_clk_0);
if (value) {
printk(KERN_ERR "Failed to enable axi clock 0\n");
goto e_clk_axi_clk_0;
}
value = clk_enable(axi_clk);
if (value) {
printk(KERN_ERR "Failed to enable axi clock 1\n");
goto e_clk_axi;
}
value = clk_enable(clock);
if (value) {
printk("Failed to enable sensor 1 clock\n");
goto e_clk_clock;
}
value = clk_set_rate(clock, thisCfg->clk);
if (value) {
printk("Failed to set sensor 1 clock\n");
goto e_clk_set_clock;
}
usleep_range(10000, 10100);
gpio_set_value(SENSOR_1_GPIO_PWRDN,
thisCfg->pwdn_active ? 0 : 1);
msleep(30);
} else {
gpio_set_value(SENSOR_1_GPIO_PWRDN, thisCfg->pwdn_active);
usleep_range(1000, 1010);
gpio_set_value(SENSOR_1_GPIO_RST, thisCfg->rst_active);
clk_disable(lp_clock_0);
clk_disable(lp_clock_1);
clk_disable(clock);
clk_disable(axi_clk);
clk_disable(axi_clk_0);
regulator_disable(d_lvldo2_cam1_1v8);
regulator_disable(d_1v8_mmc1_vcc);
regulator_disable(d_gpsr_cam0_1v8);
regulator_disable(d_3v0_mmc1_vcc);
if (pi_mgr_dfs_request_update
(&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk("Failed to set DVFS for unicam\n");
}
}
return 0;
e_clk_set_clock:
clk_disable(clock);
e_clk_clock:
clk_disable(axi_clk);
e_clk_axi:
clk_disable(axi_clk_0);
e_clk_axi_clk_0:
e_clk_set_lp1:
clk_disable(lp_clock_1);
e_clk_lp1:
e_clk_set_lp0:
clk_disable(lp_clock_0);
e_clk_lp0:
e_clk_pll:
e_clk_get:
return ret;
}
static int hawaii_camera_power(struct device *dev, int on)
{
unsigned int value;
int ret = -1;
struct clk *clock;
struct clk *prediv_clock;
struct clk *lp_clock;
struct clk *axi_clk;
static struct pi_mgr_dfs_node unicam_dfs_node;
struct soc_camera_device *icd = to_soc_camera_dev(dev);
struct soc_camera_link *icl = to_soc_camera_link(icd);
printk(KERN_INFO "%s:camera power %s\n", __func__, (on ? "on" : "off"));
struct cameraCfg_s *thisCfg = getCameraCfg(icl->module_name);
if (NULL == thisCfg) {
printk(KERN_ERR "No cfg for [%s]\n", icl->module_name);
return -1;
}
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
return -1;
}
if (gpio_request_one(SENSOR_0_GPIO_RST, GPIOF_DIR_OUT |
(thisCfg->rst_active<<1), "Cam0Rst")) {
printk(KERN_ERR "Unable to get cam0 RST GPIO\n");
return -1;
}
if (gpio_request_one(SENSOR_0_GPIO_PWRDN, GPIOF_DIR_OUT |
(thisCfg->pwdn_active<<1), "Cam0PWDN")) {
printk(KERN_ERR "Unable to get cam0 PWDN GPIO\n");
return -1;
}
#if defined(CONFIG_MACH_JAVA_C_LC1) \
|| defined(CONFIG_MACH_JAVA_C_5609A) \
|| defined(CONFIG_MACH_JAVA_C_5606)
if (gpio_request_one(MAIN_CAM_AF_ENABLE, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "Cam0_af_enable")) {
printk(KERN_ERR "Unable to get cam0 af enable GPIO\n");
return -1;
}
if (gpio_request_one(TORCH_EN, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "cam0_torch_enable")) {
printk(KERN_ERR "Unable to get cam0 torch enable GPIO\n");
return -1;
}
if (gpio_request_one(FLASH_EN, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "cam0_flash_enable")) {
printk(KERN_ERR "Unable to get cam0 torch enable GPIO\n");
return -1;
}
#endif
/*MMC1 VCC */
d_1v8_mmc1_vcc = regulator_get(NULL, icl->regulators[1].supply);
if (IS_ERR_OR_NULL(d_1v8_mmc1_vcc))
printk(KERN_ERR "Failed to get d_1v8_mmc1_vcc\n");
d_3v0_mmc1_vcc = regulator_get(NULL, icl->regulators[2].supply);
if (IS_ERR_OR_NULL(d_3v0_mmc1_vcc))
printk(KERN_ERR "Failed to get d_3v0_mmc1_vcc\n");
d_gpsr_cam0_1v8 = regulator_get(NULL,
icl->regulators[0].supply);
if (IS_ERR_OR_NULL(d_gpsr_cam0_1v8))
printk(KERN_ERR "Failed to get d_gpsr_cam0_1v8\n");
if (d_lvldo2_cam1_1v8 == NULL) {
d_lvldo2_cam1_1v8 = regulator_get(NULL,
icl->regulators[3].supply);
if (IS_ERR_OR_NULL(d_lvldo2_cam1_1v8))
printk(KERN_ERR "Fd_lvldo2_cam1_1v8 cam\n");
}
}
ret = -1;
lp_clock = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI0_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
prediv_clock = clk_get(NULL, SENSOR_PREDIV_CLK);
if (IS_ERR_OR_NULL(prediv_clock)) {
printk(KERN_ERR "Unable to get SENSOR_PREDIV_CLK clock\n");
goto e_clk_get;
}
clock = clk_get(NULL, SENSOR_0_CLK);
if (IS_ERR_OR_NULL(clock)) {
printk(KERN_ERR "Unable to get SENSOR_0 clock\n");
goto e_clk_get;
}
axi_clk = clk_get(NULL, "csi0_axi_clk");
if (IS_ERR_OR_NULL(axi_clk)) {
printk(KERN_ERR "Unable to get AXI clock\n");
goto e_clk_get;
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO))
printk("DVFS for UNICAM failed\n");
regulator_enable(d_gpsr_cam0_1v8);
usleep_range(1000, 1010);
regulator_enable(d_1v8_mmc1_vcc);
usleep_range(1000, 1010);
regulator_enable(d_lvldo2_cam1_1v8);
usleep_range(1000, 1010);
if (mm_ccu_set_pll_select(CSI0_BYTE1_PLL, 8)) {
pr_err("failed to set BYTE1\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI0_BYTE0_PLL, 8)) {
pr_err("failed to set BYTE0\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI0_CAMPIX_PLL, 8)) {
pr_err("failed to set PIXPLL\n");
goto e_clk_pll;
}
value = clk_enable(axi_clk);
if (value) {
pr_err(KERN_ERR "Failed to enable axi clock\n");
goto e_clk_axi;
}
value = clk_enable(lp_clock);
if (value) {
pr_err(KERN_ERR "Failed to enable lp clock\n");
goto e_clk_lp;
}
value = clk_set_rate(lp_clock, CSI0_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock\n");
goto e_clk_set_lp;
}
value = clk_enable(prediv_clock);
if (value) {
pr_err("Failed to enable prediv clock\n");
goto e_clk_prediv;
}
value = clk_enable(clock);
if (value) {
pr_err("Failed to enable sensor 0 clock\n");
goto e_clk_sensor;
}
value = clk_set_rate(prediv_clock, thisCfg->prediv_clk);
if (value) {
pr_err("Failed to set prediv clock\n");
goto e_clk_set_prediv;
}
value = clk_set_rate(clock, thisCfg->clk);
if (value) {
pr_err("Failed to set sensor0 clock\n");
goto e_clk_set_sensor;
}
usleep_range(10000, 10100);
gpio_set_value(SENSOR_0_GPIO_RST, thisCfg->rst_active);
usleep_range(10000, 10100);
gpio_set_value(SENSOR_0_GPIO_PWRDN,
thisCfg->pwdn_active ? 0 : 1);
usleep_range(5000, 5100);
gpio_set_value(SENSOR_0_GPIO_RST,
thisCfg->rst_active ? 0 : 1);
msleep(30);
regulator_enable(d_3v0_mmc1_vcc);
usleep_range(1000, 1010);
#if defined(CONFIG_MACH_JAVA_C_LC1) || defined(CONFIG_MACH_JAVA_C_5609A) \
|| defined(CONFIG_MACH_JAVA_C_5606)
set_af_enable(1);
#endif
#ifdef CONFIG_VIDEO_A3907
a3907_enable(1);
#endif
#ifdef CONFIG_VIDEO_DW9714
dw9714_enable(1);
#endif
} else {
#ifdef CONFIG_VIDEO_A3907
a3907_enable(0);
#endif
#ifdef CONFIG_VIDEO_DW9714
dw9714_enable(0);
#endif
#if defined(CONFIG_MACH_JAVA_C_LC1) || defined(CONFIG_MACH_JAVA_C_5609A) \
|| defined(CONFIG_MACH_JAVA_C_5606)
set_af_enable(0);
#endif
usleep_range(5000, 5100);
gpio_set_value(SENSOR_0_GPIO_PWRDN, thisCfg->pwdn_active);
usleep_range(1000, 1100);
gpio_set_value(SENSOR_0_GPIO_RST, thisCfg->rst_active);
clk_disable(prediv_clock);
clk_disable(clock);
clk_disable(lp_clock);
clk_disable(axi_clk);
regulator_disable(d_3v0_mmc1_vcc);
regulator_disable(d_lvldo2_cam1_1v8);
regulator_disable(d_1v8_mmc1_vcc);
regulator_disable(d_gpsr_cam0_1v8);
if (pi_mgr_dfs_request_update
(&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk("Failed to set DVFS for unicam\n");
}
}
return 0;
e_clk_set_sensor:
clk_disable(clock);
e_clk_sensor:
e_clk_set_prediv:
clk_disable(prediv_clock);
e_clk_prediv:
e_clk_set_lp:
clk_disable(lp_clock);
e_clk_lp:
clk_disable(axi_clk);
e_clk_axi:
e_clk_pll:
e_clk_get:
return ret;
}
static int hawaii_camera_power(struct device *dev, int on)
{
unsigned int value;
int ret = -1;
struct clk *clock;
struct clk *lp_clock;
struct clk *axi_clk;
static struct pi_mgr_dfs_node unicam_dfs_node;
struct soc_camera_device *icd = to_soc_camera_dev(dev);
struct soc_camera_link *icl = to_soc_camera_link(icd);
printk(KERN_INFO "%s:camera power %s\n", __func__, (on ? "on" : "off"));
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
return -1;
}
if (gpio_request_one(SENSOR_0_GPIO_RST, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "Cam0Rst")) {
printk(KERN_ERR "Unable to get cam0 RST GPIO\n");
return -1;
}
if (gpio_request_one(SENSOR_0_GPIO_PWRDN, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "CamPWDN")) {
printk(KERN_ERR "Unable to get cam0 PWDN GPIO\n");
return -1;
}
/*MMC1 VCC */
d_1v8_mmc1_vcc = regulator_get(NULL, icl->regulators[1].supply);
if (IS_ERR_OR_NULL(d_1v8_mmc1_vcc))
printk(KERN_ERR "Failed to get d_1v8_mmc1_vcc\n");
d_3v0_mmc1_vcc = regulator_get(NULL, icl->regulators[2].supply);
if (IS_ERR_OR_NULL(d_3v0_mmc1_vcc))
printk(KERN_ERR "Failed to get d_3v0_mmc1_vcc\n");
d_gpsr_cam0_1v8 = regulator_get(NULL,
icl->regulators[0].supply);
if (IS_ERR_OR_NULL(d_gpsr_cam0_1v8))
printk(KERN_ERR "Failed to get d_gpsr_cam0_1v8\n");
if (d_lvldo2_cam1_1v8 == NULL) {
d_lvldo2_cam1_1v8 = regulator_get(NULL,
icl->regulators[3].supply);
if (IS_ERR_OR_NULL(d_lvldo2_cam1_1v8))
printk(KERN_ERR "Fd_lvldo2_cam1_1v8 cam\n");
}
}
ret = -1;
lp_clock = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI0_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
clock = clk_get(NULL, SENSOR_0_CLK);
if (IS_ERR_OR_NULL(clock)) {
printk(KERN_ERR "Unable to get SENSOR_0 clock\n");
goto e_clk_get;
}
axi_clk = clk_get(NULL, "csi0_axi_clk");
if (IS_ERR_OR_NULL(axi_clk)) {
printk(KERN_ERR "Unable to get AXI clock\n");
goto e_clk_get;
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO))
printk("DVFS for UNICAM failed\n");
regulator_enable(d_3v0_mmc1_vcc);
usleep_range(1000, 1010);
regulator_enable(d_1v8_mmc1_vcc);
usleep_range(1000, 1010);
regulator_enable(d_gpsr_cam0_1v8);
usleep_range(1000, 1010);
regulator_enable(d_lvldo2_cam1_1v8);
usleep_range(1000, 1010);
if (mm_ccu_set_pll_select(CSI0_BYTE1_PLL, 8)) {
pr_err("failed to set BYTE1\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI0_BYTE0_PLL, 8)) {
pr_err("failed to set BYTE0\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI0_CAMPIX_PLL, 8)) {
pr_err("failed to set PIXPLL\n");
goto e_clk_pll;
}
value = clk_enable(axi_clk);
if (value) {
pr_err(KERN_ERR "Failed to enable axi clock\n");
goto e_clk_axi;
}
value = clk_enable(lp_clock);
if (value) {
pr_err(KERN_ERR "Failed to enable lp clock\n");
goto e_clk_lp;
}
value = clk_set_rate(lp_clock, CSI0_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock\n");
goto e_clk_set_lp;
}
value = clk_enable(clock);
if (value) {
pr_err("Failed to enable sensor 0 clock\n");
goto e_clk_sensor;
}
value = clk_set_rate(clock, SENSOR_0_CLK_FREQ);
if (value) {
pr_err("Failed to set sensor0 clock\n");
goto e_clk_set_sensor;
}
usleep_range(10000, 10100);
gpio_set_value(SENSOR_0_GPIO_RST, 0);
usleep_range(10000, 10100);
gpio_set_value(SENSOR_0_GPIO_PWRDN, 0);
usleep_range(5000, 5100);
gpio_set_value(SENSOR_0_GPIO_RST, 1);
msleep(30);
} else {
gpio_set_value(SENSOR_0_GPIO_RST, 0);
usleep_range(1000, 1100);
gpio_set_value(SENSOR_0_GPIO_PWRDN, 1);
clk_disable(clock);
clk_disable(lp_clock);
clk_disable(axi_clk);
regulator_disable(d_lvldo2_cam1_1v8);
regulator_disable(d_3v0_mmc1_vcc);
regulator_disable(d_1v8_mmc1_vcc);
regulator_disable(d_gpsr_cam0_1v8);
if (pi_mgr_dfs_request_update
(&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk("Failed to set DVFS for unicam\n");
}
}
return 0;
e_clk_set_sensor:
clk_disable(clock);
e_clk_sensor:
e_clk_set_lp:
clk_disable(lp_clock);
e_clk_lp:
clk_disable(axi_clk);
e_clk_axi:
e_clk_pll:
e_clk_get:
return ret;
}
