inline void im6402_device::transmit()
{
if (is_transmit_register_empty() && !m_tbre)
{
if (LOG) logerror("IM6402 '%s' Transmit Data %02x\n", tag(), m_tbr);
transmit_register_setup(m_tbr);
set_tbre(ASSERT_LINE);
set_tre(CLEAR_LINE);
}
if (!is_transmit_register_empty())
{
int bit = transmit_register_send_bit();
if (LOG) logerror("IM6402 '%s' Transmit Bit %u\n", tag(), bit);
m_out_tro_func(bit);
if (is_transmit_register_empty())
{
set_tre(ASSERT_LINE);
}
}
}
void z80dart_channel::data_write(UINT8 data)
{
m_tx_data = data;
if ((m_wr[5] & WR5_TX_ENABLE) && is_transmit_register_empty())
{
LOG(("Z80DART \"%s\" Channel %c : Transmit Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, m_tx_data));
transmit_register_setup(m_tx_data);
// empty transmit buffer
m_rr[0] |= RR0_TX_BUFFER_EMPTY;
if (m_wr[1] & WR1_TX_INT_ENABLE)
m_uart->trigger_interrupt(m_index, INT_TRANSMIT);
}
else
{
m_rr[0] &= ~RR0_TX_BUFFER_EMPTY;
}
m_rr[1] &= ~RR1_ALL_SENT;
LOG(("Z80DART \"%s\" Channel %c : Data Register Write '%02x'\n", m_owner->tag(), 'A' + m_index, data));
}
void pseudo_terminal_device::queue(void)
{
if (is_transmit_register_empty())
{
if (m_input_index == m_input_count)
{
m_input_index = 0;
int tmp = read(m_input_buffer , sizeof(m_input_buffer));
if (tmp > 0) {
m_input_count = tmp;
} else {
m_input_count = 0;
}
}
if (m_input_count != 0)
{
transmit_register_setup(m_input_buffer[ m_input_index++ ]);
m_timer_poll->adjust(attotime::never);
}
else
{
int txbaud = convert_baud(m_rs232_txbaud->read());
m_timer_poll->adjust(attotime::from_hz(txbaud));
}
}
}
void mc68901_device::tra_complete()
{
if (m_tsr & TSR_XMIT_ENABLE)
{
if (m_transmit_pending)
{
transmit_register_setup(m_transmit_buffer);
m_transmit_pending = false;
m_tsr |= TSR_BUFFER_EMPTY;
if (m_ier & IR_XMIT_BUFFER_EMPTY)
{
take_interrupt(IR_XMIT_BUFFER_EMPTY);
}
}
else
{
m_tsr |= TSR_UNDERRUN_ERROR;
// TODO: transmit error?
}
}
else
{
m_tsr |= TSR_END_OF_XMIT;
}
}
void ym3802_device::transmit_clk()
{
if(m_reg[REG_TCR] & 0x01) // Tx Enable
{
if(!m_tx_fifo.empty())
{
if (is_transmit_register_empty())
{
transmit_register_setup(m_tx_fifo.front()); // start to send first byte in FIFO
m_tx_fifo.pop(); // and remove it from the FIFO
if(m_tx_fifo.empty())
set_irq(IRQ_FIFOTX_EMPTY);
}
}
/* if diserial has bits to send, make them so */
if (!is_transmit_register_empty())
{
uint8_t data = transmit_register_get_data_bit();
m_tx_busy = true;
m_txd_handler(data);
}
if (m_tx_fifo.empty() && is_transmit_register_empty())
m_tx_busy = false;
}
}
void serial_keyboard_device::tra_complete()
{
if(m_key_valid)
{
transmit_register_setup(m_curr_key);
m_key_valid = false;
}
}
void jvc_xvd701_device::send_response()
{
if (m_response_index < sizeof(m_response) && is_transmit_register_empty())
{
// printf("sending %02x\n", m_response[m_response_index]);
transmit_register_setup(m_response[m_response_index++]);
}
}
void midi_keyboard_device::tra_complete()
{
if(m_head != m_tail)
{
transmit_register_setup(m_buffer[m_tail]);
++m_tail %= 16;
}
}
void serial_keyboard_device::send_key(UINT8 code)
{
if(is_transmit_register_empty())
{
transmit_register_setup(code);
return;
}
m_key_valid = true;
m_curr_key = code;
}
void tms5501_device::tra_complete()
{
if (!(m_sta & STA_XBE))
{
transmit_register_setup(m_tb);
m_sta |= STA_XBE;
set_interrupt(IRQ_TB);
}
}
void im6402_device::tra_complete()
{
if (!m_tbre)
{
if (LOG) logerror("IM6402 '%s' Transmit Data %02x\n", tag().c_str(), m_tbr);
transmit_register_setup(m_tbr);
set_tbre(ASSERT_LINE);
set_tre(CLEAR_LINE);
}
}
void mos6551_device::tra_complete()
{
if (!(m_st & ST_TDRE))
{
transmit_register_setup(m_tdr);
m_st |= ST_TDRE;
if ((m_cmd & CMD_TC_MASK) == CMD_TC_TIE_RTS_LO)
{
m_st |= ST_IRQ;
m_irq_handler(ASSERT_LINE);
}
}
}
void px4_state::tra_complete()
{
if (m_artsr & ART_TXRDY)
{
// no more bytes, buffer now empty
m_artsr |= ART_TXEMPTY;
}
else
{
// transfer next byte
transmit_register_setup(m_artdor);
m_artsr |= ART_TXRDY;
}
}
void snes_miracle_device::tra_complete() // Tx completed sending byte
{
// is there more waiting to send?
if (m_xmit_read != m_xmit_write)
{
transmit_register_setup(m_xmitring[m_xmit_read++]);
if (m_xmit_read >= XMIT_RING_SIZE)
{
m_xmit_read = 0;
}
}
else
{
m_tx_busy = false;
}
}
//-------------------------------------------------
// tra_complete -
//-------------------------------------------------
void z80sio_channel::tra_complete()
{
LOG("%s %s\n",FUNCNAME, tag());
if ((m_wr5 & WR5_TX_ENABLE) && !(m_wr5 & WR5_SEND_BREAK) && !(m_rr0 & RR0_TX_BUFFER_EMPTY))
{
LOG("%s() \"%s \"Channel %c Transmit Data Byte '%02x' m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_tx_data, m_wr5);
transmit_register_setup(m_tx_data);
// empty transmit buffer
m_rr0 |= RR0_TX_BUFFER_EMPTY;
if (m_wr1 & WR1_TX_INT_ENABLE)
m_uart->trigger_interrupt(m_index, INT_TRANSMIT);
}
else if (m_wr5 & WR5_SEND_BREAK)
{
LOG("%s() \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
// transmit break
if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_txda_cb(0);
else
m_uart->m_out_txdb_cb(0);
}
else
{
LOG("%s() \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
// transmit mark
if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_txda_cb(1);
else
m_uart->m_out_txdb_cb(1);
}
// if transmit buffer is empty
if (m_rr0 & RR0_TX_BUFFER_EMPTY)
{
LOG("%s() \"%s \"Channel %c Transmit buffer empty m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5);
// then all characters have been sent
m_rr1 |= RR1_ALL_SENT;
// when the RTS bit is reset, the _RTS output goes high after the transmitter empties
if (!m_rts)
set_rts(1);
}
}
void midiin_device::tra_complete()
{
// is there more waiting to send?
if (m_xmit_read != m_xmit_write)
{
// printf("tx1 %02x\n", m_xmitring[m_xmit_read]);
transmit_register_setup(m_xmitring[m_xmit_read++]);
if (m_xmit_read >= XMIT_RING_SIZE)
{
m_xmit_read = 0;
}
}
else
{
m_tx_busy = false;
}
}
void sb_device::tra_complete() // Tx completed sending byte
{
// printf("Tx complete\n");
// is there more waiting to send?
if (m_tx_waiting)
{
transmit_register_setup(m_xmitring[m_xmit_read++]);
if (m_xmit_read >= MIDI_RING_SIZE)
{
m_xmit_read = 0;
}
m_tx_waiting--;
}
else
{
m_tx_busy = false;
}
}
void apollo_kbd_device::xmit_char(UINT8 data)
{
// if tx is busy it'll pick this up automatically when it completes
if (!m_tx_busy)
{
m_tx_busy = true;
transmit_register_setup(data);
}
else
{
// tx is busy, it'll pick this up next time
m_xmitring[m_xmit_write++] = data;
if (m_xmit_write >= XMIT_RING_SIZE)
{
m_xmit_write = 0;
}
}
}
void nes_miracle_device::xmit_char(uint8_t data)
{
// if tx is busy it'll pick this up automatically when it completes
// if not, send now!
if (!m_tx_busy)
{
m_tx_busy = true;
transmit_register_setup(data);
}
else
{
// tx is busy, it'll pick this up next time
m_xmitring[m_xmit_write++] = data;
if (m_xmit_write >= XMIT_RING_SIZE)
{
m_xmit_write = 0;
}
}
}
void z80dart_channel::tra_complete()
{
if ((m_wr[5] & WR5_TX_ENABLE) && !(m_wr[5] & WR5_SEND_BREAK) && !(m_rr[0] & RR0_TX_BUFFER_EMPTY))
{
LOG(("Z80DART \"%s\" Channel %c : Transmit Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, m_tx_data));
transmit_register_setup(m_tx_data);
// empty transmit buffer
m_rr[0] |= RR0_TX_BUFFER_EMPTY;
if (m_wr[1] & WR1_TX_INT_ENABLE)
m_uart->trigger_interrupt(m_index, INT_TRANSMIT);
}
else if (m_wr[5] & WR5_SEND_BREAK)
{
// transmit break
if (m_index == z80dart_device::CHANNEL_A)
m_uart->m_out_txda_cb(0);
else
m_uart->m_out_txdb_cb(0);
}
else
{
// transmit mark
if (m_index == z80dart_device::CHANNEL_A)
m_uart->m_out_txda_cb(1);
else
m_uart->m_out_txdb_cb(1);
}
// if transmit buffer is empty
if (m_rr[0] & RR0_TX_BUFFER_EMPTY)
{
// then all characters have been sent
m_rr[1] |= RR1_ALL_SENT;
// when the RTS bit is reset, the _RTS output goes high after the transmitter empties
if (!m_rts)
set_rts(1);
}
}
void midiin_device::xmit_char(UINT8 data)
{
// printf("MIDI in: xmit %02x\n", data);
// if tx is busy it'll pick this up automatically when it completes
if (!m_tx_busy)
{
m_tx_busy = true;
// printf("tx0 %02x\n", data);
transmit_register_setup(data);
}
else
{
// tx is busy, it'll pick this up next time
m_xmitring[m_xmit_write++] = data;
if (m_xmit_write >= XMIT_RING_SIZE)
{
m_xmit_write = 0;
}
}
}
void sb_device::xmit_char(uint8_t data)
{
// printf("SB: xmit %02x\n", data);
// if tx is busy it'll pick this up automatically when it completes
if (!m_tx_busy)
{
m_tx_busy = true;
transmit_register_setup(data);
}
else
{
// tx is busy, it'll pick this up next time
m_xmitring[m_xmit_write++] = data;
if (m_xmit_write >= MIDI_RING_SIZE)
{
m_xmit_write = 0;
}
m_tx_waiting++;
}
}
inline void im6402_device::transmit()
{
if (is_transmit_register_empty() && !m_tbre)
{
transmit_register_setup(m_tbr);
set_tbre(ASSERT_LINE);
set_tre(CLEAR_LINE);
}
if (!is_transmit_register_empty())
{
int bit = transmit_register_get_data_bit();
m_out_tro_func(bit);
serial_connection_out();
if (is_transmit_register_empty())
{
set_tre(ASSERT_LINE);
}
}
}
void null_modem_device::queue()
{
if (is_transmit_register_empty())
{
if (m_input_index == m_input_count)
{
m_input_index = 0;
m_input_count = m_stream->input(m_input_buffer, sizeof(m_input_buffer));
}
if (m_input_count != 0)
{
transmit_register_setup(m_input_buffer[m_input_index++]);
m_timer_poll->adjust(attotime::never);
}
else
{
int txbaud = convert_baud(m_rs232_txbaud->read());
m_timer_poll->adjust(attotime::from_hz(txbaud));
}
}
}
//-------------------------------------------------
// data_write - write data register
//-------------------------------------------------
void z80sio_channel::data_write(uint8_t data)
{
m_tx_data = data;
if ((m_wr5 & WR5_TX_ENABLE) && is_transmit_register_empty())
{
LOG("Z80SIO \"%s\" Channel %c : Transmit Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, m_tx_data);
transmit_register_setup(m_tx_data);
// empty transmit buffer
m_rr0 |= RR0_TX_BUFFER_EMPTY;
if (m_wr1 & WR1_TX_INT_ENABLE)
m_uart->trigger_interrupt(m_index, INT_TRANSMIT);
}
else
{
LOG(" Transmitter %s, data byte dropped\n", m_wr5 & WR5_TX_ENABLE ? "not enabled" : "not emptied");
m_rr0 &= ~RR0_TX_BUFFER_EMPTY;
}
m_rr1 &= ~RR1_ALL_SENT;
}
void mc68901_device::register_w(offs_t offset, uint8_t data)
{
switch (offset)
{
case REGISTER_GPIP:
LOG("MC68901 General Purpose I/O : %x\n", data);
m_gpip = data;
gpio_output();
break;
case REGISTER_AER:
LOG("MC68901 Active Edge Register : %x\n", data);
m_aer = data;
break;
case REGISTER_DDR:
LOG("MC68901 Data Direction Register : %x\n", data);
m_ddr = data;
gpio_output();
break;
case REGISTER_IERA:
LOG("MC68901 Interrupt Enable Register A : %x\n", data);
m_ier = (data << 8) | (m_ier & 0xff);
m_ipr &= m_ier;
check_interrupts();
break;
case REGISTER_IERB:
LOG("MC68901 Interrupt Enable Register B : %x\n", data);
m_ier = (m_ier & 0xff00) | data;
m_ipr &= m_ier;
check_interrupts();
break;
case REGISTER_IPRA:
LOG("MC68901 Interrupt Pending Register A : %x\n", data);
m_ipr &= (data << 8) | (m_ipr & 0xff);
check_interrupts();
break;
case REGISTER_IPRB:
LOG("MC68901 Interrupt Pending Register B : %x\n", data);
m_ipr &= (m_ipr & 0xff00) | data;
check_interrupts();
break;
case REGISTER_ISRA:
LOG("MC68901 Interrupt In-Service Register A : %x\n", data);
m_isr &= (data << 8) | (m_isr & 0xff);
break;
case REGISTER_ISRB:
LOG("MC68901 Interrupt In-Service Register B : %x\n", data);
m_isr &= (m_isr & 0xff00) | data;
break;
case REGISTER_IMRA:
LOG("MC68901 Interrupt Mask Register A : %x\n", data);
m_imr = (data << 8) | (m_imr & 0xff);
m_isr &= m_imr;
check_interrupts();
break;
case REGISTER_IMRB:
LOG("MC68901 Interrupt Mask Register B : %x\n", data);
m_imr = (m_imr & 0xff00) | data;
m_isr &= m_imr;
check_interrupts();
break;
case REGISTER_VR:
LOG("MC68901 Interrupt Vector : %x\n", data & 0xf0);
m_vr = data & 0xf8;
if (m_vr & VR_S)
{
LOG("MC68901 Software End-Of-Interrupt Mode\n");
}
else
{
LOG("MC68901 Automatic End-Of-Interrupt Mode\n");
m_isr = 0;
}
break;
case REGISTER_TACR:
m_tacr = data & 0x1f;
switch (m_tacr & 0x0f)
{
case TCR_TIMER_STOPPED:
LOG("MC68901 Timer A Stopped\n");
m_timer[TIMER_A]->enable(false);
break;
case TCR_TIMER_DELAY_4:
case TCR_TIMER_DELAY_10:
case TCR_TIMER_DELAY_16:
case TCR_TIMER_DELAY_50:
case TCR_TIMER_DELAY_64:
case TCR_TIMER_DELAY_100:
case TCR_TIMER_DELAY_200:
{
int divisor = PRESCALER[m_tacr & 0x07];
LOG("MC68901 Timer A Delay Mode : %u Prescale\n", divisor);
m_timer[TIMER_A]->adjust(attotime::from_hz(m_timer_clock / divisor), 0, attotime::from_hz(m_timer_clock / divisor));
}
break;
case TCR_TIMER_EVENT:
LOG("MC68901 Timer A Event Count Mode\n");
m_timer[TIMER_A]->enable(false);
break;
case TCR_TIMER_PULSE_4:
case TCR_TIMER_PULSE_10:
case TCR_TIMER_PULSE_16:
case TCR_TIMER_PULSE_50:
case TCR_TIMER_PULSE_64:
case TCR_TIMER_PULSE_100:
case TCR_TIMER_PULSE_200:
{
int divisor = PRESCALER[m_tacr & 0x07];
LOG("MC68901 Timer A Pulse Width Mode : %u Prescale\n", divisor);
m_timer[TIMER_A]->adjust(attotime::never, 0, attotime::from_hz(m_timer_clock / divisor));
m_timer[TIMER_A]->enable(false);
}
break;
}
if (m_tacr & TCR_TIMER_RESET)
{
LOG("MC68901 Timer A Reset\n");
m_to[TIMER_A] = 0;
m_out_tao_cb(m_to[TIMER_A]);
}
break;
case REGISTER_TBCR:
m_tbcr = data & 0x1f;
switch (m_tbcr & 0x0f)
{
case TCR_TIMER_STOPPED:
LOG("MC68901 Timer B Stopped\n");
m_timer[TIMER_B]->enable(false);
break;
case TCR_TIMER_DELAY_4:
case TCR_TIMER_DELAY_10:
case TCR_TIMER_DELAY_16:
case TCR_TIMER_DELAY_50:
case TCR_TIMER_DELAY_64:
case TCR_TIMER_DELAY_100:
case TCR_TIMER_DELAY_200:
{
int divisor = PRESCALER[m_tbcr & 0x07];
LOG("MC68901 Timer B Delay Mode : %u Prescale\n", divisor);
m_timer[TIMER_B]->adjust(attotime::from_hz(m_timer_clock / divisor), 0, attotime::from_hz(m_timer_clock / divisor));
}
break;
case TCR_TIMER_EVENT:
LOG("MC68901 Timer B Event Count Mode\n");
m_timer[TIMER_B]->enable(false);
break;
case TCR_TIMER_PULSE_4:
case TCR_TIMER_PULSE_10:
case TCR_TIMER_PULSE_16:
case TCR_TIMER_PULSE_50:
case TCR_TIMER_PULSE_64:
case TCR_TIMER_PULSE_100:
case TCR_TIMER_PULSE_200:
{
int divisor = PRESCALER[m_tbcr & 0x07];
LOG("MC68901 Timer B Pulse Width Mode : %u Prescale\n", DIVISOR);
m_timer[TIMER_B]->adjust(attotime::never, 0, attotime::from_hz(m_timer_clock / divisor));
m_timer[TIMER_B]->enable(false);
}
break;
}
if (m_tacr & TCR_TIMER_RESET)
{
LOG("MC68901 Timer B Reset\n");
m_to[TIMER_B] = 0;
m_out_tbo_cb(m_to[TIMER_B]);
}
break;
case REGISTER_TCDCR:
m_tcdcr = data & 0x77;
switch (m_tcdcr & 0x07)
{
case TCR_TIMER_STOPPED:
LOG("MC68901 Timer D Stopped\n");
m_timer[TIMER_D]->enable(false);
break;
case TCR_TIMER_DELAY_4:
case TCR_TIMER_DELAY_10:
case TCR_TIMER_DELAY_16:
case TCR_TIMER_DELAY_50:
case TCR_TIMER_DELAY_64:
case TCR_TIMER_DELAY_100:
case TCR_TIMER_DELAY_200:
{
int divisor = PRESCALER[m_tcdcr & 0x07];
LOG("MC68901 Timer D Delay Mode : %u Prescale\n", divisor);
m_timer[TIMER_D]->adjust(attotime::from_hz(m_timer_clock / divisor), 0, attotime::from_hz(m_timer_clock / divisor));
}
break;
}
switch ((m_tcdcr >> 4) & 0x07)
{
case TCR_TIMER_STOPPED:
LOG("MC68901 Timer C Stopped\n");
m_timer[TIMER_C]->enable(false);
break;
case TCR_TIMER_DELAY_4:
case TCR_TIMER_DELAY_10:
case TCR_TIMER_DELAY_16:
case TCR_TIMER_DELAY_50:
case TCR_TIMER_DELAY_64:
case TCR_TIMER_DELAY_100:
case TCR_TIMER_DELAY_200:
{
int divisor = PRESCALER[(m_tcdcr >> 4) & 0x07];
LOG("MC68901 Timer C Delay Mode : %u Prescale\n", divisor);
m_timer[TIMER_C]->adjust(attotime::from_hz(m_timer_clock / divisor), 0, attotime::from_hz(m_timer_clock / divisor));
}
break;
}
break;
case REGISTER_TADR:
LOG("MC68901 Timer A Data Register : %x\n", data);
m_tdr[TIMER_A] = data;
if (!m_timer[TIMER_A]->enabled())
{
m_tmc[TIMER_A] = data;
}
break;
case REGISTER_TBDR:
LOG("MC68901 Timer B Data Register : %x\n", data);
m_tdr[TIMER_B] = data;
if (!m_timer[TIMER_B]->enabled())
{
m_tmc[TIMER_B] = data;
}
break;
case REGISTER_TCDR:
LOG("MC68901 Timer C Data Register : %x\n", data);
m_tdr[TIMER_C] = data;
if (!m_timer[TIMER_C]->enabled())
{
m_tmc[TIMER_C] = data;
}
break;
case REGISTER_TDDR:
LOG("MC68901 Timer D Data Register : %x\n", data);
m_tdr[TIMER_D] = data;
if (!m_timer[TIMER_D]->enabled())
{
m_tmc[TIMER_D] = data;
}
break;
case REGISTER_SCR:
LOG("MC68901 Sync Character : %x\n", data);
m_scr = data;
break;
case REGISTER_UCR:
{
int data_bit_count;
switch (data & 0x60)
{
case UCR_WORD_LENGTH_8: default: data_bit_count = 8; break;
case UCR_WORD_LENGTH_7: data_bit_count = 7; break;
case UCR_WORD_LENGTH_6: data_bit_count = 6; break;
case UCR_WORD_LENGTH_5: data_bit_count = 5; break;
}
parity_t parity;
if (data & UCR_PARITY_ENABLED)
{
if (data & UCR_PARITY_EVEN)
{
LOG("MC68901 Parity : Even\n");
parity = PARITY_EVEN;
}
else
{
LOG("MC68901 Parity : Odd\n");
parity = PARITY_ODD;
}
}
else
{
LOG("MC68901 Parity : Disabled\n");
parity = PARITY_NONE;
}
LOG("MC68901 Word Length : %u bits\n", data_bit_count);
int start_bits;
stop_bits_t stop_bits;
switch (data & 0x18)
{
case UCR_START_STOP_0_0:
default:
start_bits = 0;
stop_bits = STOP_BITS_0;
LOG("MC68901 Start Bits : 0, Stop Bits : 0, Format : synchronous\n");
break;
case UCR_START_STOP_1_1:
start_bits = 1;
stop_bits = STOP_BITS_1;
LOG("MC68901 Start Bits : 1, Stop Bits : 1, Format : asynchronous\n");
break;
case UCR_START_STOP_1_15:
start_bits = 1;
stop_bits = STOP_BITS_1_5;
LOG("MC68901 Start Bits : 1, Stop Bits : 1.5, Format : asynchronous\n");
break;
case UCR_START_STOP_1_2:
start_bits = 1;
stop_bits = STOP_BITS_2;
LOG("MC68901 Start Bits : 1, Stop Bits : 2, Format : asynchronous\n");
break;
}
if (data & UCR_CLOCK_DIVIDE_16)
{
LOG("MC68901 Rx/Tx Clock Divisor : 16\n");
}
else
{
LOG("MC68901 Rx/Tx Clock Divisor : 1\n");
}
set_data_frame(start_bits, data_bit_count, parity, stop_bits);
receive_register_reset();
m_ucr = data;
}
break;
case REGISTER_RSR:
if ((data & RSR_RCV_ENABLE) == 0)
{
LOG("MC68901 Receiver Disabled\n");
m_rsr = 0;
}
else
{
LOG("MC68901 Receiver Enabled\n");
if (data & RSR_SYNC_STRIP_ENABLE)
{
LOG("MC68901 Sync Strip Enabled\n");
}
else
{
LOG("MC68901 Sync Strip Disabled\n");
}
if (data & RSR_FOUND_SEARCH)
LOG("MC68901 Receiver Search Mode Enabled\n");
m_rsr = data & 0x0b;
}
break;
case REGISTER_TSR:
m_tsr = (m_tsr & (TSR_BUFFER_EMPTY | TSR_UNDERRUN_ERROR | TSR_END_OF_XMIT)) | (data & ~(TSR_BUFFER_EMPTY | TSR_UNDERRUN_ERROR | TSR_END_OF_XMIT));
if ((data & TSR_XMIT_ENABLE) == 0)
{
LOG("MC68901 Transmitter Disabled\n");
m_tsr &= ~TSR_UNDERRUN_ERROR;
if (is_transmit_register_empty())
m_tsr |= TSR_END_OF_XMIT;
}
else
{
LOG("MC68901 Transmitter Enabled\n");
switch (data & 0x06)
{
case TSR_OUTPUT_HI_Z:
LOG("MC68901 Transmitter Disabled Output State : Hi-Z\n");
break;
case TSR_OUTPUT_LOW:
LOG("MC68901 Transmitter Disabled Output State : 0\n");
break;
case TSR_OUTPUT_HIGH:
LOG("MC68901 Transmitter Disabled Output State : 1\n");
break;
case TSR_OUTPUT_LOOP:
LOG("MC68901 Transmitter Disabled Output State : Loop\n");
break;
}
if (data & TSR_BREAK)
{
LOG("MC68901 Transmitter Break Enabled\n");
}
else
{
LOG("MC68901 Transmitter Break Disabled\n");
}
if (data & TSR_AUTO_TURNAROUND)
{
LOG("MC68901 Transmitter Auto Turnaround Enabled\n");
}
else
{
LOG("MC68901 Transmitter Auto Turnaround Disabled\n");
}
m_tsr &= ~TSR_END_OF_XMIT;
if (m_transmit_pending && is_transmit_register_empty())
{
transmit_register_setup(m_transmit_buffer);
m_transmit_pending = false;
}
if (!m_transmit_pending)
m_tsr |= TSR_BUFFER_EMPTY;
}
break;
case REGISTER_UDR:
LOG("MC68901 UDR %x\n", data);
m_transmit_buffer = data;
m_transmit_pending = true;
m_tsr &= ~TSR_BUFFER_EMPTY;
if ((m_tsr & TSR_XMIT_ENABLE) && is_transmit_register_empty())
{
transmit_register_setup(m_transmit_buffer);
m_transmit_pending = false;
m_tsr |= TSR_BUFFER_EMPTY;
}
break;
}
}
/*-------------------------------------------------
start_tx
-------------------------------------------------*/
void i8251_device::start_tx()
{
transmit_register_setup(m_tx_data);
m_status &= ~I8251_STATUS_TX_EMPTY;
m_status |= I8251_STATUS_TX_READY;
}
void graph_link_hle_device::byte_received(u8 data)
{
transmit_register_setup(data);
}
void i8251_device::transmit_clock()
{
/* transmit enable? */
if (m_command & (1<<0))
{
/* transmit register full? */
if ((m_status & I8251_STATUS_TX_READY)==0)
{
/* if transmit reg is empty */
if (is_transmit_register_empty())
{
/* set it up */
transmit_register_setup(m_data);
/* i8251 transmit reg now empty */
m_status |=I8251_STATUS_TX_EMPTY;
/* ready for next transmit */
m_status |=I8251_STATUS_TX_READY;
update_tx_empty();
update_tx_ready();
}
}
/* if transmit is not empty... transmit data */
if (!is_transmit_register_empty())
{
UINT8 data = transmit_register_get_data_bit();
// logerror("I8251\n");
//transmit_register_send_bit();
m_out_txd_func(data);
m_connection_state &=~SERIAL_STATE_TX_DATA;
m_connection_state|=(data<<5);
serial_connection_out();
}
}
#if 0
/* hunt mode? */
/* after each bit has been shifted in, it is compared against the current sync byte */
if (m_command & (1<<7))
{
/* data matches sync byte? */
if (m_data == m_sync_bytes[m_sync_byte_offset])
{
/* sync byte matches */
/* update for next sync byte? */
m_sync_byte_offset++;
/* do all sync bytes match? */
if (m_sync_byte_offset == m_sync_byte_count)
{
/* ent hunt mode */
m_command &=~(1<<7);
}
}
else
{
/* if there is no match, reset */
m_sync_byte_offset = 0;
}
}
#endif
}
void i8251_device::transmit_clock()
{
m_txc_count++;
if (m_txc_count == m_br_factor)
m_txc_count = 0;
else
return;
/* transmit enabled? */
if (m_command & (1<<0))
{
/* do we have a character to send? */
if ((m_status & I8251_STATUS_TX_READY)==0)
{
/* is diserial ready for it? */
if (is_transmit_register_empty())
{
/* set it up */
transmit_register_setup(m_data);
/* i8251 transmit reg now empty */
m_status |=I8251_STATUS_TX_EMPTY;
/* ready for next transmit */
m_status |=I8251_STATUS_TX_READY;
update_tx_empty();
update_tx_ready();
}
}
/* if diserial has bits to send, make them so */
if (!is_transmit_register_empty())
{
UINT8 data = transmit_register_get_data_bit();
m_tx_busy = true;
m_txd_handler(data);
}
// is transmitter totally done?
if ((m_status & I8251_STATUS_TX_READY) && is_transmit_register_empty())
{
m_tx_busy = false;
if (m_disable_tx_pending)
{
LOG(("Applying pending disable\n"));
m_disable_tx_pending = false;
m_command &= ~(1<<0);
m_txd_handler(1);
update_tx_ready();
}
}
}
#if 0
/* hunt mode? */
/* after each bit has been shifted in, it is compared against the current sync byte */
if (m_command & (1<<7))
{
/* data matches sync byte? */
if (m_data == m_sync_bytes[m_sync_byte_offset])
{
/* sync byte matches */
/* update for next sync byte? */
m_sync_byte_offset++;
/* do all sync bytes match? */
if (m_sync_byte_offset == m_sync_byte_count)
{
/* ent hunt mode */
m_command &=~(1<<7);
}
}
else
{
/* if there is no match, reset */
m_sync_byte_offset = 0;
}
}
#endif
}
