static int tsb_spi_resume(struct device *dev)
{
struct tsb_spi_dev_info *info;
info = device_get_private(dev);
tsb_clk_enable(TSB_CLK_SPIP);
tsb_clk_enable(TSB_CLK_SPIS);
info->spi_pmstate = PM_NORMAL;
return 0;
}
static int data_load_mmapped_init(void) {
if (initialized != 1) {
current_addr = (uint8_t*) MMAP_LOAD_BASE;
initialized = 1;
/* enable SPI master clock.
Pinshare should be default to SPI (CS0) after reset */
tsb_clk_enable(TSB_CLK_SPIP);
tsb_clk_enable(TSB_CLK_SPIS);
return 0;
}
return -1;
}
/**
* @brief Initialize SPI controller
*
* @param info pointer to the tsb_spi_dev_info struct.
* @return 0 on success, negative errno on error
*/
static int tsb_spi_hw_init(struct tsb_spi_dev_info *info)
{
uint32_t ctrl0;
int ret = 0;
/* Enable clock */
tsb_clk_enable(TSB_CLK_SPIP);
tsb_clk_enable(TSB_CLK_SPIS);
/* Reset */
tsb_reset(TSB_RST_SPIP);
tsb_reset(TSB_RST_SPIS);
info->spi_pmstate = PM_NORMAL;
/* Disable SPI controller */
tsb_spi_write(info->reg_base, DW_SPI_SSIENR, 0);
/* Disable SPI all interrupts */
tsb_spi_write(info->reg_base, DW_SPI_IMR, 0);
/* Clear interrupt status register */
tsb_spi_read(info->reg_base, DW_SPI_ICR);
/* SPI supports both transmit and receiver mode */
ctrl0 = tsb_spi_read(info->reg_base, DW_SPI_CTRLR0);
ctrl0 &= ~SPI_CTRL0_TMOD_MASK;
tsb_spi_write(info->reg_base, DW_SPI_CTRLR0, ctrl0);
/* get SPIM_CLK, SPIM_SDI and SPIM_SDO */
ret = tsb_pin_request(PIN_SPIM);
if (ret) {
lowsyslog("SPI: cannot get ownership of PIN_SPIM\n");
goto err_req_pinshare;
}
#if !defined(CONFIG_TSB_SPI_GPIO)
/* get also SPIM_CS0_N and SPIM_CS1_N */
ret = tsb_pin_request(PIN_SPIM_CSX_N);
if (ret) {
lowsyslog("SPI: cannot get ownership of PIN_SPIM_CSX_N\n");
goto err_req_pinshare_gpio;
}
#endif
return 0;
err_req_pinshare_gpio:
tsb_pin_release(PIN_SPIM);
err_req_pinshare:
return ret;
}
struct cdsi_dev *cdsi_initialize(int cdsi, int tx)
{
struct cdsi_dev *dev;
dev = malloc(sizeof(struct cdsi_dev));
if (!dev)
return NULL;
dev->tx = tx;
dev->base = cdsi == TSB_CDSI0 ? CDSI0_BASE : CDSI1_BASE;
tsb_clk_enable(cdsi == TSB_CDSI0 ? TSB_CLK_CDSI0_REF : TSB_CLK_CDSI1_REF);
#if CONFIG_ARCH_VIDCRYPT
tsb_clk_enable(TSB_CLK_VIDENCRYPT);
tsb_reset(TSB_RST_VIDCRYPTIF);
tsb_reset(TSB_RST_VIDCRYPTCH0);
tsb_reset(TSB_RST_VIDCRYPTCH1);
#endif
if (tx) {
if (cdsi == TSB_CDSI0) {
tsb_clk_enable(TSB_CLK_CDSI0_TX_SYS);
tsb_clk_enable(TSB_CLK_CDSI0_TX_APB);
tsb_reset(TSB_RST_CDSI0_TX);
tsb_reset(TSB_RST_CDSI0_TX_AIO);
} else {
tsb_clk_enable(TSB_CLK_CDSI1_TX_SYS);
tsb_clk_enable(TSB_CLK_CDSI1_TX_APB);
tsb_reset(TSB_RST_CDSI1_TX);
tsb_reset(TSB_RST_CDSI1_TX_AIO);
}
} else {
if (cdsi == TSB_CDSI0) {
tsb_clk_enable(TSB_CLK_CDSI0_RX_SYS);
tsb_clk_enable(TSB_CLK_CDSI0_RX_APB);
tsb_reset(TSB_RST_CDSI0_RX);
tsb_reset(TSB_RST_CDSI0_RX_AIO);
} else {
tsb_clk_enable(TSB_CLK_CDSI1_RX_SYS);
tsb_clk_enable(TSB_CLK_CDSI1_RX_APB);
tsb_reset(TSB_RST_CDSI1_RX);
tsb_reset(TSB_RST_CDSI1_RX_AIO);
}
}
#if CONFIG_ARCH_VIDCRYPT
tsb_vidcrypt_set_mode(cdsi, tx);
tsb_vidcrypt_enable(cdsi);
#endif
return dev;
}
void tsb_dma_init_controller(struct device *dev)
{
// enable clock to GDMAC and reset GDMAC.
tsb_clk_enable (TSB_CLK_GDMA);
tsb_reset (TSB_RST_GDMA);
tsb_dma_gdmac_dev = dev;
}
static struct cdsi_dev *cdsi_initialize(int cdsi, int tx)
{
struct cdsi_dev *dev;
dev = malloc(sizeof(struct cdsi_dev));
if (!dev)
return NULL;
dev->tx = tx;
dev->base = cdsi == TSB_CDSI0 ? CDSI0_BASE : CDSI1_BASE;
tsb_clk_enable(cdsi == TSB_CDSI0 ? TSB_CLK_CDSI0_REF : TSB_CLK_CDSI1_REF);
if (tx) {
if (cdsi == TSB_CDSI0) {
tsb_clk_enable(TSB_CLK_CDSI0_TX_SYS);
tsb_clk_enable(TSB_CLK_CDSI0_TX_APB);
tsb_reset(TSB_RST_CDSI0_TX);
tsb_reset(TSB_RST_CDSI0_TX_AIO);
} else {
tsb_clk_enable(TSB_CLK_CDSI1_TX_SYS);
tsb_clk_enable(TSB_CLK_CDSI1_TX_APB);
tsb_reset(TSB_RST_CDSI1_TX);
tsb_reset(TSB_RST_CDSI1_TX_AIO);
}
} else {
if (cdsi == TSB_CDSI0) {
tsb_clk_enable(TSB_CLK_CDSI0_RX_SYS);
tsb_clk_enable(TSB_CLK_CDSI0_RX_APB);
tsb_reset(TSB_RST_CDSI0_RX);
tsb_reset(TSB_RST_CDSI0_RX_AIO);
} else {
tsb_clk_enable(TSB_CLK_CDSI1_RX_SYS);
tsb_clk_enable(TSB_CLK_CDSI1_RX_APB);
tsb_reset(TSB_RST_CDSI1_RX);
tsb_reset(TSB_RST_CDSI1_RX_AIO);
}
}
return dev;
}
void chip_gpio_init(void) {
tsb_clk_enable(TSB_CLK_GPIO);
tsb_reset(TSB_RST_GPIO);
}
/**
* Initialise an I2C device
*/
struct i2c_dev_s *up_i2cinitialize(int port)
{
irqstate_t flags;
int retval;
i2cvdbg("Init I2C port %d\n", port);
/* Only one I2C port on TSB */
if (port > 0)
return NULL;
flags = irqsave();
if (refcount++)
goto out;
retval = tsb_request_pinshare(TSB_PIN_GPIO21 | TSB_PIN_GPIO22);
if (retval) {
lowsyslog("I2C: cannot get ownership of I2C pins\n");
goto err_req_pinshare;
}
sem_init(&g_mutex, 0, 1);
sem_init(&g_wait, 0, 0);
/* enable I2C pins */
tsb_clr_pinshare(TSB_PIN_GPIO21);
tsb_clr_pinshare(TSB_PIN_GPIO22);
/* enable I2C clocks */
tsb_clk_enable(TSB_CLK_I2CP);
tsb_clk_enable(TSB_CLK_I2CS);
/* reset I2C module */
tsb_reset(TSB_RST_I2CP);
tsb_reset(TSB_RST_I2CS);
/* Initialize the I2C controller */
tsb_i2c_init();
/* Allocate a watchdog timer */
g_timeout = wd_create();
DEBUGASSERT(g_timeout != 0);
/* Attach Interrupt Handler */
irq_attach(TSB_IRQ_I2C, i2c_interrupt);
/* Enable Interrupt Handler */
up_enable_irq(TSB_IRQ_I2C);
/* Install our operations */
g_dev.ops = &dev_i2c_ops;
out:
irqrestore(flags);
return &g_dev;
err_req_pinshare:
refcount--;
irqrestore(flags);
return NULL;
}
