static void __init v2m_dt_timer_init(void) { struct device_node *node = NULL; of_clk_init(NULL); do { node = of_find_compatible_node(node, NULL, "arm,sp804"); } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB); if (node) { pr_info("Using SP804 '%s' as a clock & events source\n", node->full_name); WARN_ON(clk_register_clkdev(of_clk_get_by_name(node, "timclken1"), "v2m-timer0", "sp804")); WARN_ON(clk_register_clkdev(of_clk_get_by_name(node, "timclken2"), "v2m-timer1", "sp804")); v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0)); } if (arch_timer_of_register() != 0) twd_local_timer_of_register(); if (arch_timer_sched_clock_init() != 0) versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), 24000000); }
static void __init ux500_twd_init(void) { struct twd_local_timer *twd_local_timer; int err; /* Use this to switch local timer base if changed in new ASICs */ twd_local_timer = &u8500_twd_local_timer; if (of_have_populated_dt()) twd_local_timer_of_register(); else { err = twd_local_timer_register(twd_local_timer); if (err) pr_err("twd_local_timer_register failed %d\n", err); } }
static void __init omap4_local_timer_init(void) { omap4_sync32k_timer_init(); /* Local timers are not supprted on OMAP4430 ES1.0 */ if (omap_rev() != OMAP4430_REV_ES1_0) { int err; if (of_have_populated_dt()) { twd_local_timer_of_register(); return; } err = twd_local_timer_register(&twd_local_timer); if (err) pr_err("twd_local_timer_register failed %d\n", err); } }
static void __init omap4_timer_init(void) { omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); omap2_clocksource_init(2, OMAP4_MPU_SOURCE); #ifdef CONFIG_LOCAL_TIMERS /* Local timers are not supprted on OMAP4430 ES1.0 */ if (omap_rev() != OMAP4430_REV_ES1_0) { int err; if (of_have_populated_dt()) { twd_local_timer_of_register(); return; } err = twd_local_timer_register(&twd_local_timer); if (err) pr_err("twd_local_timer_register failed %d\n", err); } #endif }
static void __init v2m_dt_timer_init(void) { struct device_node *node; const char *path; int err; node = of_find_compatible_node(NULL, NULL, "arm,sp810"); v2m_sysctl_init(of_iomap(node, 0)); v2m_clk_init(); err = of_property_read_string(of_aliases, "arm,v2m_timer", &path); if (WARN_ON(err)) return; node = of_find_node_by_path(path); v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0)); if (arch_timer_of_register() != 0) twd_local_timer_of_register(); if (arch_timer_sched_clock_init() != 0) versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000); }
/** * xttcps_timer_init - Initialize the timer * * Initializes the timer hardware and register the clock source and clock event * timers with Linux kernal timer framework */ static void __init xttcps_timer_init(struct device_node *timer) { unsigned int irq; void __iomem *timer_baseaddr; struct clk *clk; /* * Get the 1st Triple Timer Counter (TTC) block from the device tree * and use it. Note that the event timer uses the interrupt and it's the * 2nd TTC hence the irq_of_parse_and_map(,1) */ timer_baseaddr = of_iomap(timer, 0); if (!timer_baseaddr) { pr_err("ERROR: invalid timer base address\n"); BUG(); } irq = irq_of_parse_and_map(timer, 1); if (irq <= 0) { pr_err("ERROR: invalid interrupt number\n"); BUG(); } clk = clk_get_sys("CPU_1X_CLK", NULL); if (IS_ERR(clk)) { pr_err("ERROR: timer input clock not found\n"); BUG(); } zynq_ttc_setup_clocksource(clk, timer_baseaddr); zynq_ttc_setup_clockevent(clk, timer_baseaddr + 4, irq); #ifdef CONFIG_HAVE_ARM_TWD twd_local_timer_of_register(); #endif pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); }
static void __init tegra20_init_timer(void) { struct device_node *np; struct clk *clk; unsigned long rate; int ret; np = of_find_matching_node(NULL, timer_match); if (!np) { pr_err("Failed to find timer DT node\n"); BUG(); } timer_reg_base = of_iomap(np, 0); if (!timer_reg_base) { pr_err("Can't map timer registers\n"); BUG(); } tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); if (tegra_timer_irq.irq <= 0) { pr_err("Failed to map timer IRQ\n"); BUG(); } clk = of_clk_get(np, 0); if (IS_ERR(clk)) { pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); rate = 12000000; } else { clk_prepare_enable(clk); rate = clk_get_rate(clk); } of_node_put(np); np = of_find_matching_node(NULL, rtc_match); if (!np) { pr_err("Failed to find RTC DT node\n"); BUG(); } rtc_base = of_iomap(np, 0); if (!rtc_base) { pr_err("Can't map RTC registers"); BUG(); } /* * rtc registers are used by read_persistent_clock, keep the rtc clock * enabled */ clk = of_clk_get(np, 0); if (IS_ERR(clk)) pr_warn("Unable to get rtc-tegra clock\n"); else clk_prepare_enable(clk); of_node_put(np); switch (rate) { case 12000000: timer_writel(0x000b, TIMERUS_USEC_CFG); break; case 13000000: timer_writel(0x000c, TIMERUS_USEC_CFG); break; case 19200000: timer_writel(0x045f, TIMERUS_USEC_CFG); break; case 26000000: timer_writel(0x0019, TIMERUS_USEC_CFG); break; default: WARN(1, "Unknown clock rate"); } setup_sched_clock(tegra_read_sched_clock, 32, 1000000); if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { pr_err("Failed to register clocksource\n"); BUG(); } ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); if (ret) { pr_err("Failed to register timer IRQ: %d\n", ret); BUG(); } tegra_clockevent.cpumask = cpu_all_mask; tegra_clockevent.irq = tegra_timer_irq.irq; clockevents_config_and_register(&tegra_clockevent, 1000000, 0x1, 0x1fffffff); #ifdef CONFIG_HAVE_ARM_TWD twd_local_timer_of_register(); #endif register_persistent_clock(NULL, tegra_read_persistent_clock); }
static void __init imx6q_timer_init(void) { mx6q_clocks_init(); twd_local_timer_of_register(); }
static void __init imx6q_timer_init(void) { mx6q_clocks_init(); twd_local_timer_of_register(); imx_print_silicon_rev("i.MX6Q", imx6q_revision()); }