/**
* Configure TWI
* @param config
*/
void twiConfig(const twiConfigT *config) {
uint32_t divisor;
uint8_t prescale;
if (config->master != twi.modeMaster)
twiReset();
if (config->freq) {
divisor = (sysclk_get_pba_hz() + 2 * config->freq - 1) / (2 * config->freq);
if (divisor > 4) {
divisor -= 4;
} else {
divisor = 0;
}
prescale = 0;
while (divisor > 0xff && prescale <= 7) {
divisor = (divisor + 1) >> 1;
prescale++;
}
if (divisor <= 0xff && prescale <= 7) {
AVR32_TWI.cwgr = (divisor << AVR32_TWI_CWGR_CLDIV_OFFSET) | (divisor << AVR32_TWI_CWGR_CHDIV_OFFSET) | ((uint32_t) prescale <<
AVR32_TWI_CWGR_CKDIV_OFFSET);
}
}
//Write a value to a register
//pre: register_addre is the register to write to
// value is the value to place in the register
//returns: 1-Success
// TWSR- Failure
//usage status=gyro.write(register_addr, value);
char cITG3200::write(char register_addr, char value){
twiReset();
return twiTransmit(_i2c_address, register_addr, value);
}
//Read a register value from the gyro
//pre: register_addr is the register address to read
// value is a pointer to an integer
//post: value contains the value of the register that was read
//returns: 1-Success
// TWSR-Failure (Check out twi.h for TWSR error codes)
//usage: status = gyro.read(DEVID, &value); //value is created as an 'int' in main.cpp
char cITG3200::read(char register_addr, char * value){
twiReset();
return twiReceive(_i2c_address, register_addr, value);
}
/**
* Periodic task
*/
static void masterHandler(void) {
static twiRequestT req;
static enum {
idleTS = 0,
queryRegulatorTemperature1TS,
waitForRegulatorTemperature1TS,
queryRegulatorTemperature2TS,
waitForRegulatorTemperature2TS,
queryRegulatorFailCodesTS,
waitForRegulatorFailCodesTS,
queryRegulatorCurrentFaultTS,
waitForRegulatorCurrentFaultTS,
queryRegulatorPhaseFaultTS,
waitForRegulatorPhaseFaultTS,
queryInputVoltageTS,
waitForInputVoltageTS,
queryOutputVoltageTS,
waitForOutputVoltageTS,
queryBoardTempsTS,
waitForBoardTempsTS,
queryTachsTS,
waitForTachsTS,
queryPowerStatusTS,
waitForPowerStatusTS
} state;
static enum {
resetBS = 0,
idleBS,
retrySubmitBS,
busyBS
} busState[TWI_BUS_COUNT];
static uint16_t lastModulePoll;
static uint16_t lastIRPoll;
static uint16_t watchdog[TWI_BUS_COUNT];
static uint8_t txBuffer[16];
static uint8_t rxBuffer[32];
static uint8_t slave;
static uint8_t ir;
static int16_t temperature;
int status;
uint16_t v;
uint8_t i;
spiFpgaTwiMasterHandler();
for (i = 0; i < TWI_BUS_COUNT; i++) {
if (masterRequestHead[i]) {
switch (busState[i]) {
case resetBS:
switch (i) {
case TWI_BUS_UC:
twiReset();
twi_master_setup();
break;
case TWI_BUS_FPGA:
spiFpgaTwiReset();
break;
}
busState[i] = idleBS;
break;
case idleBS:
/* fall through */
case retrySubmitBS:
switch (i) {
case TWI_BUS_UC:
status = twiMasterWriteRead(masterRequestHead[TWI_BUS_UC]->addr, masterRequestHead[TWI_BUS_UC]->tx, masterRequestHead[TWI_BUS_UC]->txLength, masterRequestHead[TWI_BUS_UC]->rx, masterRequestHead[TWI_BUS_UC]->rxLength);
break;
case TWI_BUS_FPGA:
status = spiFpgaTwiMasterWriteRead(masterRequestHead[TWI_BUS_FPGA]->addr, masterRequestHead[TWI_BUS_FPGA]->tx, masterRequestHead[TWI_BUS_FPGA]->txLength, masterRequestHead[TWI_BUS_FPGA]->rx, masterRequestHead[TWI_BUS_FPGA]->rxLength);
break;
}
if (status == TWI_SUCCESS) {
busState[i] = busyBS;
watchdog[i] = msec_ticker;
} else {
if (busState[i] == idleBS) {
watchdog[i] = msec_ticker;
busState[i] = retrySubmitBS;
} else if (elapsed_since(watchdog[i]) > TWI_TIME_MAX) {
masterRequestHead[i]->result = status;
masterRequestHead[i]->pending = 0;
masterRequestHead[i] = masterRequestHead[i]->next;
busState[i] = resetBS;
}
}
break;
case busyBS:
switch (i) {
case TWI_BUS_UC:
status = twiStatus();
break;
case TWI_BUS_FPGA:
status = spiFpgaTwiStatus();
break;
}
if (status != TWI_BUSY) {
masterRequestHead[i]->result = status;
masterRequestHead[i]->pending = 0;
masterRequestHead[i] = masterRequestHead[i]->next;
busState[i] = idleBS;
} else if (elapsed_since(watchdog[i]) > TWI_TIME_MAX) {
masterRequestHead[i]->result = TWI_TIMEOUT;
masterRequestHead[i]->pending = 0;
masterRequestHead[i] = masterRequestHead[i]->next;
busState[i] = resetBS;
}
break;
}
}
}
switch (state) {
case idleTS:
if (boardid == iraBID &&
elapsed_since(lastIRPoll) >= TWI_IR_POLLING_INTERVAL) {
lastIRPoll = msec_ticker;
ir = 0;
state = queryRegulatorTemperature1TS;
} else if (ucinfo.master && ucinfo.num_slaves &&
elapsed_since(lastModulePoll) >=
TWI_MODULE_POLLING_INTERVAL) {
lastModulePoll = msec_ticker;
slave = 0;
state = queryBoardTempsTS;
}
break;
/*
* Regulator Temperature 1
*/
case queryRegulatorTemperature1TS:
txBuffer[0] = IR3566B_REG_TEMP1;
req.addr = TWI_IR3566B_STARTADDR + ir;
req.tx = txBuffer;
req.txLength = 1;
req.rx = rxBuffer;
req.rxLength = 1;
twiQueueRequest(TWI_BUS_IR3566B, &req);
state = waitForRegulatorTemperature1TS;
break;
case waitForRegulatorTemperature1TS:
if (!req.pending) {
if (req.result == TWI_SUCCESS)
temperature = rxBuffer[0];
else
temperature = -1;
state = queryRegulatorTemperature2TS;
}
break;
/*
* Regulator Temperature 2
*/
case queryRegulatorTemperature2TS:
txBuffer[0] = IR3566B_REG_TEMP2;
req.addr = TWI_IR3566B_STARTADDR + ir;
req.tx = txBuffer;
req.txLength = 1;
req.rx = rxBuffer;
req.rxLength = 1;
twiQueueRequest(TWI_BUS_IR3566B, &req);
state = waitForRegulatorTemperature2TS;
break;
case waitForRegulatorTemperature2TS:
if (!req.pending) {
if (req.result == TWI_SUCCESS) {
if ((int16_t) rxBuffer[0] > temperature)
temperature = rxBuffer[0];
}
if (temperature >= 0)
gwq_update_board_temperature(ir, 0x1000 | (uint16_t) temperature);
state = queryRegulatorFailCodesTS;
}
break;
/*
* Regulator Fail Codes
*/
case queryRegulatorFailCodesTS:
txBuffer[0] = IR3566B_REG_L1_FAIL;
req.addr = TWI_IR3566B_STARTADDR + ir;
req.tx = txBuffer;
req.txLength = 1;
req.rx = rxBuffer;
req.rxLength = 1;
twiQueueRequest(TWI_BUS_IR3566B, &req);
state = waitForRegulatorFailCodesTS;
break;
case waitForRegulatorFailCodesTS:
if (!req.pending) {
if (req.result == TWI_SUCCESS) {
if (rxBuffer[0]) {
/* a failure code is pending */
if (rxBuffer[0] & IR3566B_REG_L1_FAIL_OVER_TEMP)
usbctrlDebugStreamPrintf("Regulator %d Fail: Over Temp\n", ir);
if (rxBuffer[0] & IR3566B_REG_L1_FAIL_OVER_CURRENT)
usbctrlDebugStreamPrintf("Regulator %d Fail: Over Current\n", ir);
if (rxBuffer[0] & IR3566B_REG_L1_FAIL_VCPU_HIGH)
usbctrlDebugStreamPrintf("Regulator %d Fail: VCPU High\n", ir);
if (rxBuffer[0] & IR3566B_REG_L1_FAIL_VCPU_LOW)
usbctrlDebugStreamPrintf("Regulator %d Fail: VCPU Low\n", ir);
if (rxBuffer[0] & IR3566B_REG_L1_FAIL_V12_LOW)
usbctrlDebugStreamPrintf("Regulator %d Fail: V12 Low\n", ir);
if (rxBuffer[0] & IR3566B_REG_L1_FAIL_V3_LOW)
usbctrlDebugStreamPrintf("Regulator %d Fail: V3 Low\n", ir);
if (rxBuffer[0] & IR3566B_REG_L1_FAIL_PHASE_FAULT)
usbctrlDebugStreamPrintf("Regulator %d Fail: Phase Fault\n", ir);
if (rxBuffer[0] & IR3566B_REG_L1_FAIL_SLOW_OVER_CURRENT)
usbctrlDebugStreamPrintf("Regulator %d Fail: Slow Over Current\n", ir);
/* clear sticky codes */
txBuffer[0] = IR3566B_REG_CLEAR_FAIL;
txBuffer[1] = IR3566B_REG_CLEAR_FAIL_L1_STICKY;
req.addr = TWI_IR3566B_STARTADDR + ir;
req.tx = txBuffer;
req.txLength = 2;
req.rx = rxBuffer;
req.rxLength = 0;
twiQueueRequest(TWI_BUS_IR3566B, &req);
}
}
state = queryRegulatorCurrentFaultTS;
}
break;
/*
* Regulator Current Fault
*/
case queryRegulatorCurrentFaultTS:
txBuffer[0] = IR3566B_REG_L1_CURRENT_FAULT;
req.addr = TWI_IR3566B_STARTADDR + ir;
req.tx = txBuffer;
req.txLength = 1;
req.rx = rxBuffer;
req.rxLength = 1;
twiQueueRequest(TWI_BUS_IR3566B, &req);
state = waitForRegulatorCurrentFaultTS;
break;
case waitForRegulatorCurrentFaultTS:
if (!req.pending) {
if (req.result == TWI_SUCCESS) {
if ((rxBuffer[0] & IR3566B_REG_L1_CURRENT_FAULT_MAX) || (rxBuffer[0] & IR3566B_REG_L1_CURRENT_FAULT_MIN)) {
/* a failure code is pending */
if (rxBuffer[0] & IR3566B_REG_L1_CURRENT_FAULT_MIN)
usbctrlDebugStreamPrintf("Regulator %d Current Fault: Min\n", ir);
if (rxBuffer[0] & IR3566B_REG_L1_CURRENT_FAULT_MAX)
usbctrlDebugStreamPrintf("Regulator %d Current Fault: Max\n", ir);
/* read the phase that is generating the fault */
state = queryRegulatorPhaseFaultTS;
} else {
/* move to next statistic */
state = queryInputVoltageTS;
}
}
}
break;
/*
* Regulator Phase Fault
*/
case queryRegulatorPhaseFaultTS:
txBuffer[0] = IR3566B_REG_PHASE_FAULT;
req.addr = TWI_IR3566B_STARTADDR + ir;
req.tx = txBuffer;
req.txLength = 1;
req.rx = rxBuffer;
req.rxLength = 1;
twiQueueRequest(TWI_BUS_IR3566B, &req);
state = waitForRegulatorPhaseFaultTS;
break;
case waitForRegulatorPhaseFaultTS:
if (!req.pending) {
if (req.result == TWI_SUCCESS) {
/* report which phase is generating the fault */
if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE1)
usbctrlDebugStreamWriteStr("Fault in Phase 1\n");
if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE2)
usbctrlDebugStreamWriteStr("Fault in Phase 2\n");
if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE3)
usbctrlDebugStreamWriteStr("Fault in Phase 3\n");
if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE4)
usbctrlDebugStreamWriteStr("Fault in Phase 4\n");
if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE5)
usbctrlDebugStreamWriteStr("Fault in Phase 5\n");
if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE6)
usbctrlDebugStreamWriteStr("Fault in Phase 6\n");
if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE7)
usbctrlDebugStreamWriteStr("Fault in Phase 7\n");
/* clear the phase fault */
txBuffer[0] = IR3566B_REG_CLEAR_PHASE_FAULT;
txBuffer[1] = IR3566B_REG_CLEAR_PHASE_FAULT_BIT;
req.addr = TWI_IR3566B_STARTADDR + ir;
req.tx = txBuffer;
req.txLength = 2;
req.rx = rxBuffer;
req.rxLength = 0;
twiQueueRequest(TWI_BUS_IR3566B, &req);
}
state = queryInputVoltageTS;
}
break;
/*
* Regulator Input Voltage
*/
case queryInputVoltageTS:
txBuffer[0] = IR3566B_REG_VIN_SUPPLY;
req.addr = TWI_IR3566B_STARTADDR + ir;
req.tx = txBuffer;
req.txLength = 1;
req.rx = rxBuffer;
req.rxLength = 1;
twiQueueRequest(TWI_BUS_IR3566B, &req);
state = waitForInputVoltageTS;
break;
case waitForInputVoltageTS:
if (!req.pending) {
if (req.result == TWI_SUCCESS)
moduleStatus[0].inputMillivolts[ir] = (uint16_t) ((uint32_t) rxBuffer[0] * 1000 / 8);
state = queryOutputVoltageTS;
}
break;
/*
* Regulator Output Voltage
*/
case queryOutputVoltageTS:
txBuffer[0] = IR3566B_REG_L1_VOUT;
req.addr = TWI_IR3566B_STARTADDR + ir;
req.tx = txBuffer;
req.txLength = 1;
req.rx = rxBuffer;
req.rxLength = 1;
twiQueueRequest(TWI_BUS_IR3566B, &req);
state = waitForOutputVoltageTS;
break;
case waitForOutputVoltageTS:
if (!req.pending) {
if (req.result == TWI_SUCCESS) {
moduleStatus[0].outputMillivolts[ir] = (uint16_t) ((uint32_t) rxBuffer[0] * 1000 / 128);
}
if (++ir < 4) {
state = queryRegulatorTemperature1TS;
} else {
state = idleTS;
}
}
break;
/*
* Board Temperatures
*/
case queryBoardTempsTS:
txBuffer[0] = TWICMD_BOARD_TEMPERATURES;
req.addr = TWI_SLAVE_STARTADDR + slave;
req.tx = txBuffer;
req.txLength = 1;
req.rx = rxBuffer;
req.rxLength = 8;
twiQueueRequest(TWI_BUS_UC, &req);
state = waitForBoardTempsTS;
break;
case waitForBoardTempsTS:
if (!req.pending) {
if (req.result == TWI_SUCCESS) {
for (i = 0; i < 4; i++) {
v = ((uint16_t) rxBuffer[i * 2 + 0] << 8) | rxBuffer[i * 2 + 1];
gwq_update_board_temperature((slave + 1) * 4 + i, v);
}
}
state = queryTachsTS;
}
break;
/*
* Board Tachs
*/
case queryTachsTS:
txBuffer[0] = TWICMD_TACHS;
req.addr = TWI_SLAVE_STARTADDR + slave;
req.tx = txBuffer;
req.txLength = 1;
req.rx = rxBuffer;
req.rxLength = 8;
twiQueueRequest(TWI_BUS_UC, &req);
state = waitForTachsTS;
break;
case waitForTachsTS:
if (!req.pending) {
if (req.result == TWI_SUCCESS) {
for (i = 0; i < 4; i++) {
v = ((uint16_t) rxBuffer[i * 2 + 0] << 8) | rxBuffer[i * 2 + 1];
gwq_update_tach((slave + 1) * 4 + i, v);
}
}
state = queryPowerStatusTS;
}
break;
/*
* Board Power Status
*/
case queryPowerStatusTS:
txBuffer[0] = TWICMD_POWER_STATUS;
req.addr = TWI_SLAVE_STARTADDR + slave;
req.tx = txBuffer;
req.txLength = 1;
req.rx = rxBuffer;
req.rxLength = 18;
twiQueueRequest(TWI_BUS_UC, &req);
state = waitForPowerStatusTS;
break;
case waitForPowerStatusTS:
if (!req.pending) {
if (req.result == TWI_SUCCESS) {
for (i = 0; i < 4; i++) {
v = ((uint16_t) rxBuffer[i * 4 + 2] << 8) | rxBuffer[i * 4 + 3];
moduleStatus[slave + 1].inputMillivolts[i] = v;
v = ((uint16_t) rxBuffer[i * 4 + 4] << 8) | rxBuffer[i * 4 + 5];
moduleStatus[slave + 1].outputMillivolts[i] = v;
}
}
if (++slave < ucinfo.num_slaves)
state = queryBoardTempsTS;
else
state = idleTS;
}
break;
}
}
/**
* Initialize TWI
*/
void twiInit(void) {
twiReset();
INTC_register_interrupt(&twiInterrupt, AVR32_TWI_IRQ, AVR32_INTC_INT0);
}
