コード例 #1
0
/*******************************************************************************
 * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
 * and allow Non-Secure masters full access.
 ******************************************************************************/
static void init_tzc400(void)
{
	unsigned long long region_base, region_top;
	unsigned long long ddr_base = STM32MP_DDR_BASE;
	unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size();
	unsigned long long ddr_top = ddr_base + (ddr_size - 1U);

	tzc400_init(STM32MP1_TZC_BASE);

	tzc400_disable_filters();

#ifdef AARCH32_SP_OPTEE
	/*
	 * Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the
	 * same configuration to all filters in the TZC.
	 */
	region_base = ddr_base;
	region_top = ddr_top - STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE;
	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
				region_base,
				region_top,
				TZC_REGION_S_NONE,
				TZC_REGION_NSEC_ALL_ACCESS_RDWR);

	/* Region 2 set to cover all secure DRAM. */
	region_base = region_top + 1U;
	region_top = ddr_top - STM32MP_DDR_SHMEM_SIZE;
	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 2,
				region_base,
				region_top,
				TZC_REGION_S_RDWR,
				0);

	/* Region 3 set to cover non-secure shared memory DRAM. */
	region_base = region_top + 1U;
	region_top = ddr_top;
	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 3,
				region_base,
				region_top,
				TZC_REGION_S_NONE,
				TZC_REGION_NSEC_ALL_ACCESS_RDWR);
#else
	/*
	 * Region 1 set to cover all DRAM at 0xC000_0000. Apply the
	 * same configuration to all filters in the TZC.
	 */
	region_base = ddr_base;
	region_top = ddr_top;
	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
				region_base,
				region_top,
				TZC_REGION_S_NONE,
				TZC_REGION_NSEC_ALL_ACCESS_RDWR);
#endif

	/* Raise an exception if a NS device tries to access secure memory */
	tzc400_set_action(TZC_ACTION_ERR);

	tzc400_enable_filters();
}
コード例 #2
0
/*******************************************************************************
 * Initialize the TrustZone Controller for ARM standard platforms.
 * Configure:
 *   - Region 0 with no access;
 *   - Region 1 with secure access only;
 *   - the remaining DRAM regions access from the given Non-Secure masters.
 *
 * When booting an EL3 payload, this is simplified: we configure region 0 with
 * secure access only and do not enable any other region.
 ******************************************************************************/
void arm_tzc400_setup(void)
{
	INFO("Configuring TrustZone Controller\n");

	tzc400_init(PLAT_ARM_TZC_BASE);

	/* Disable filters. */
	tzc400_disable_filters();

#ifndef EL3_PAYLOAD_BASE

	/* Region 0 set to no access by default */
	tzc400_configure_region0(TZC_REGION_S_NONE, 0);

	/* Region 1 set to cover Secure part of DRAM */
	tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 1,
			ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END,
			TZC_REGION_S_RDWR,
			0);

	/* Region 2 set to cover Non-Secure access to 1st DRAM address range.
	 * Apply the same configuration to given filters in the TZC. */
	tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 2,
			ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END,
			ARM_TZC_NS_DRAM_S_ACCESS,
			PLAT_ARM_TZC_NS_DEV_ACCESS);

	/* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
	tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 3,
			ARM_DRAM2_BASE, ARM_DRAM2_END,
			ARM_TZC_NS_DRAM_S_ACCESS,
			PLAT_ARM_TZC_NS_DEV_ACCESS);
#else
	/* Allow secure access only to DRAM for EL3 payloads. */
	tzc400_configure_region0(TZC_REGION_S_RDWR, 0);
#endif /* EL3_PAYLOAD_BASE */

	/*
	 * Raise an exception if a NS device tries to access secure memory
	 * TODO: Add interrupt handling support.
	 */
	tzc400_set_action(TZC_ACTION_ERR);

	/* Enable filters. */
	tzc400_enable_filters();
}
コード例 #3
0
/*******************************************************************************
 * Initialize the TrustZone Controller.
 * Early initialization create only one region with full access to secure.
 * This setting is used before and during DDR initialization.
 ******************************************************************************/
static void early_init_tzc400(void)
{
	stm32mp_clk_enable(TZC1);
	stm32mp_clk_enable(TZC2);

	tzc400_init(STM32MP1_TZC_BASE);

	tzc400_disable_filters();

	/* Region 1 set to cover Non-Secure DRAM at 0xC000_0000 */
	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
				STM32MP_DDR_BASE,
				STM32MP_DDR_BASE +
				(STM32MP_DDR_MAX_SIZE - 1U),
				TZC_REGION_S_NONE,
				TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
				TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID));

	/* Raise an exception if a NS device tries to access secure memory */
	tzc400_set_action(TZC_ACTION_ERR);

	tzc400_enable_filters();
}