uint8_t u8g_com_raspberrypi_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
{
switch(msg)
{
case U8G_COM_MSG_STOP:
break;
case U8G_COM_MSG_INIT:
// check wiringPi setup
if (wiringPiSetup() == -1)
{
printf("wiringPi-Error\n");
exit(1);
}
if (wiringPiSPISetup (0, 100000) < 0)
{
printf ("Unable to open SPI device 0: %s\n", strerror (errno)) ;
exit (1) ;
}
u8g_SetPIOutput(u8g, U8G_PI_RESET);
u8g_SetPIOutput(u8g, U8G_PI_A0);
break;
case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
u8g_SetPILevel(u8g, U8G_PI_A0, arg_val);
break;
case U8G_COM_MSG_CHIP_SELECT:
/* Done by the SPI hardware */
break;
case U8G_COM_MSG_RESET:
u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val);
break;
case U8G_COM_MSG_WRITE_BYTE:
wiringPiSPIDataRW (0, &arg_val, 1) ;
break;
case U8G_COM_MSG_WRITE_SEQ:
wiringPiSPIDataRW (0, arg_ptr, arg_val);
break;
case U8G_COM_MSG_WRITE_SEQ_P:
wiringPiSPIDataRW (0, arg_ptr, arg_val);
break;
}
return 1;
}
uint8_t u8g_com_stm32duino_fsmc_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr) {
if (msgInitCount) {
if (msg == U8G_COM_MSG_INIT) msgInitCount--;
if (msgInitCount) return -1;
}
static uint8_t isCommand;
switch (msg) {
case U8G_COM_MSG_STOP:
break;
case U8G_COM_MSG_INIT:
u8g_SetPIOutput(u8g, U8G_PI_RESET);
LCD_IO_Init(u8g->pin_list[U8G_PI_CS], u8g->pin_list[U8G_PI_A0]);
u8g_Delay(100);
if (arg_ptr != NULL)
*((uint32_t *)arg_ptr) = LCD_IO_ReadData(LCD_READ_ID, 3);
isCommand = 0;
break;
case U8G_COM_MSG_ADDRESS: // define cmd (arg_val = 0) or data mode (arg_val = 1)
isCommand = arg_val == 0 ? 1 : 0;
break;
case U8G_COM_MSG_RESET:
u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val);
break;
case U8G_COM_MSG_WRITE_BYTE:
if (isCommand)
LCD_IO_WriteReg(arg_val);
else
LCD_IO_WriteData((uint16_t)arg_val);
break;
case U8G_COM_MSG_WRITE_SEQ:
for (uint8_t i = 0; i < arg_val; i += 2)
LCD_IO_WriteData(*(uint16_t *)(((uint32_t)arg_ptr) + i));
break;
}
return 1;
}
uint8_t u8g_com_atmega_st7920_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
{
switch(msg)
{
case U8G_COM_MSG_INIT:
u8g_SetPIOutput(u8g, U8G_PI_CS);
//u8g_SetPIOutput(u8g, U8G_PI_A0);
U8G_ATOMIC_START();
DDRB |= U8G_ATMEGA_HW_SPI_MOSI_PIN;
DDRB |= U8G_ATMEGA_HW_SPI_SCK_PIN;
DDRB |= U8G_ATMEGA_HW_SPI_SLAVE_SELECT_PIN;
PORTB &= ~U8G_ATMEGA_HW_SPI_MOSI_PIN;
PORTB &= ~U8G_ATMEGA_HW_SPI_SCK_PIN;
U8G_ATOMIC_END();
u8g_SetPILevel(u8g, U8G_PI_CS, 1);
/*
SPR1 SPR0
0 0 fclk/4
0 1 fclk/16
1 0 fclk/64
1 1 fclk/128
*/
SPCR = 0;
/* maybe set CPOL and CPHA to 1 */
/* 20 Dez 2012: did set CPOL and CPHA to 1 in Arduino variant! */
/* 24 Jan 2014: implemented, see also issue 221 */
SPCR = (1<<SPE) | (1<<MSTR)|(0<<SPR1)|(0<<SPR0)|(1<<CPOL)|(1<<CPHA);
#ifdef U8G_HW_SPI_2X
SPSR = (1 << SPI2X); /* double speed, issue 89 */
#endif
u8g->pin_list[U8G_PI_A0_STATE] = 0; /* inital RS state: command mode */
break;
case U8G_COM_MSG_STOP:
break;
case U8G_COM_MSG_RESET:
u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val);
break;
case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
u8g->pin_list[U8G_PI_A0_STATE] = arg_val;
break;
case U8G_COM_MSG_CHIP_SELECT:
if ( arg_val == 0 )
{
/* disable, note: the st7920 has an active high chip select */
u8g_SetPILevel(u8g, U8G_PI_CS, 0);
}
else
{
/* u8g_SetPILevel(u8g, U8G_PI_SCK, 0 ); */
/* enable */
u8g_SetPILevel(u8g, U8G_PI_CS, 1); /* CS = 1 (high active) */
}
break;
case U8G_COM_MSG_WRITE_BYTE:
u8g_com_atmega_st7920_write_byte_hw_spi(u8g, u8g->pin_list[U8G_PI_A0_STATE], arg_val);
//u8g->pin_list[U8G_PI_A0_STATE] = 2;
break;
case U8G_COM_MSG_WRITE_SEQ:
{
register uint8_t *ptr = arg_ptr;
while( arg_val > 0 )
{
u8g_com_atmega_st7920_write_byte_hw_spi(u8g, u8g->pin_list[U8G_PI_A0_STATE], *ptr++);
//u8g->pin_list[U8G_PI_A0_STATE] = 2;
arg_val--;
}
}
break;
case U8G_COM_MSG_WRITE_SEQ_P:
{
register uint8_t *ptr = arg_ptr;
while( arg_val > 0 )
{
u8g_com_atmega_st7920_write_byte_hw_spi(u8g, u8g->pin_list[U8G_PI_A0_STATE], u8g_pgm_read(ptr));
//u8g->pin_list[U8G_PI_A0_STATE] = 2;
ptr++;
arg_val--;
}
}
break;
}
return 1;
}
uint8_t u8g_com_atxmega_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
{
switch(msg)
{
case U8G_COM_MSG_STOP:
break;
case U8G_COM_MSG_INIT:
u8g_SetPIOutput(u8g, U8G_PI_CS);
u8g_SetPIOutput(u8g, U8G_PI_A0);
u8g_SetPIOutput(u8g, U8G_PI_RESET);
//U8G_ATOMIC_START();
PORTC.DIR |= PIN4_bm | PIN5_bm | PIN7_bm;
PORTC.DIR &= ~PIN6_bm;
//U8G_ATOMIC_END();
u8g_SetPILevel(u8g, U8G_PI_CS, 1);
SPIC.CTRL = 0;
SPIC.CTRL = SPI_PRESCALER_DIV4_gc | // SPI prescaler.
//SPI_CLK2X_bm | //SPI Clock double.
SPI_ENABLE_bm | //Enable SPI module.
//SPI_DORD_bm | //Data order.
SPI_MASTER_bm | //SPI master.
SPI_MODE_0_gc; // SPI mode.
#ifdef U8G_HW_SPI_2X
SPIC.CTRL |= SPI_CLK2X_bm; /* double speed, issue 89 */
#endif
break;
case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
u8g_SetPILevel(u8g, U8G_PI_A0, arg_val);
break;
case U8G_COM_MSG_CHIP_SELECT:
if ( arg_val == 0 )
{
/* disable */
u8g_SetPILevel(u8g, U8G_PI_CS, 1);
}
else
{
//PORTB &= ~_BV(5); /* SCK = 0 */
PORTC.OUT &= ~PIN7_bm;
/* enable */
u8g_SetPILevel(u8g, U8G_PI_CS, 0); /* CS = 0 (low active) */
}
break;
case U8G_COM_MSG_RESET:
u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val);
break;
case U8G_COM_MSG_WRITE_BYTE:
u8g_atxmega_spi_out(arg_val);
break;
case U8G_COM_MSG_WRITE_SEQ:
{
register uint8_t *ptr = arg_ptr;
while( arg_val > 0 )
{
u8g_atxmega_spi_out(*ptr++);
arg_val--;
}
}
break;
case U8G_COM_MSG_WRITE_SEQ_P:
{
register uint8_t *ptr = arg_ptr;
while( arg_val > 0 )
{
u8g_atxmega_spi_out(u8g_pgm_read(ptr));
ptr++;
arg_val--;
}
}
break;
}
return 1;
}
uint8_t u8g_com_atmega_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
{
switch(msg)
{
case U8G_COM_MSG_STOP:
break;
case U8G_COM_MSG_INIT:
u8g_SetPIOutput(u8g, U8G_PI_CS);
u8g_SetPIOutput(u8g, U8G_PI_A0);
DDRB |= _BV(3); /* D0, MOSI */
DDRB |= _BV(5); /* SCK */
PORTB &= ~_BV(3); /* D0, MOSI = 0 */
PORTB &= ~_BV(5); /* SCK = 0 */
u8g_SetPILevel(u8g, U8G_PI_CS, 1);
/*
SPR1 SPR0
0 0 fclk/4
0 1 fclk/16
1 0 fclk/64
1 1 fclk/128
*/
SPCR = 0;
SPCR = (1<<SPE) | (1<<MSTR)|(0<<SPR1)|(0<<SPR0)|(0<<CPOL)|(0<<CPHA);
break;
case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
u8g_SetPILevel(u8g, U8G_PI_A0, arg_val);
break;
case U8G_COM_MSG_CHIP_SELECT:
if ( arg_val == 0 )
{
/* disable */
u8g_SetPILevel(u8g, U8G_PI_CS, 1);
}
else
{
PORTB &= ~_BV(5); /* SCK = 0 */
/* enable */
u8g_SetPILevel(u8g, U8G_PI_CS, 0); /* CS = 0 (low active) */
}
break;
case U8G_COM_MSG_RESET:
u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val);
break;
case U8G_COM_MSG_WRITE_BYTE:
u8g_atmega_spi_out(arg_val);
break;
case U8G_COM_MSG_WRITE_SEQ:
{
register uint8_t *ptr = arg_ptr;
while( arg_val > 0 )
{
u8g_atmega_spi_out(*ptr++);
arg_val--;
}
}
break;
case U8G_COM_MSG_WRITE_SEQ_P:
{
register uint8_t *ptr = arg_ptr;
while( arg_val > 0 )
{
u8g_atmega_spi_out(u8g_pgm_read(ptr));
ptr++;
arg_val--;
}
}
break;
}
return 1;
}
uint8_t u8g_com_atxmega_st7920_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
{
switch(msg)
{
case U8G_COM_MSG_INIT:
u8g_SetPIOutput(u8g, U8G_PI_CS);
//u8g_SetPIOutput(u8g, U8G_PI_A0);
//U8G_ATOMIC_START();
PORTC.DIR |= PIN4_bm | PIN5_bm | PIN7_bm;
PORTC.DIR &= ~PIN6_bm;
//U8G_ATOMIC_END();
u8g_SetPILevel(u8g, U8G_PI_CS, 1);
SPIC.CTRL = 0;
SPIC.CTRL = SPI_PRESCALER_DIV4_gc | // SPI prescaler.
//SPI_CLK2X_bm | //SPI Clock double.
SPI_ENABLE_bm | //Enable SPI module.
//SPI_DORD_bm | //Data order.
SPI_MASTER_bm | //SPI master.
SPI_MODE_0_gc; // SPI mode.
#ifdef U8G_HW_SPI_2X
SPIC.CTRL |= SPI_CLK2X_bm; /* double speed, issue 89 */
#endif
u8g->pin_list[U8G_PI_A0_STATE] = 0; /* inital RS state: command mode */
break;
case U8G_COM_MSG_STOP:
break;
case U8G_COM_MSG_RESET:
u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val);
break;
case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
u8g->pin_list[U8G_PI_A0_STATE] = arg_val;
break;
case U8G_COM_MSG_CHIP_SELECT:
if ( arg_val == 0 )
{
/* disable, note: the st7920 has an active high chip select */
u8g_SetPILevel(u8g, U8G_PI_CS, 0);
}
else
{
/* u8g_SetPILevel(u8g, U8G_PI_SCK, 0 ); */
/* enable */
u8g_SetPILevel(u8g, U8G_PI_CS, 1); /* CS = 1 (high active) */
}
break;
case U8G_COM_MSG_WRITE_BYTE:
u8g_com_atxmega_st7920_write_byte_hw_spi(u8g, u8g->pin_list[U8G_PI_A0_STATE], arg_val);
//u8g->pin_list[U8G_PI_A0_STATE] = 2;
break;
case U8G_COM_MSG_WRITE_SEQ:
{
register uint8_t *ptr = arg_ptr;
while( arg_val > 0 )
{
u8g_com_atxmega_st7920_write_byte_hw_spi(u8g, u8g->pin_list[U8G_PI_A0_STATE], *ptr++);
//u8g->pin_list[U8G_PI_A0_STATE] = 2;
arg_val--;
}
}
break;
case U8G_COM_MSG_WRITE_SEQ_P:
{
register uint8_t *ptr = arg_ptr;
while( arg_val > 0 )
{
u8g_com_atxmega_st7920_write_byte_hw_spi(u8g, u8g->pin_list[U8G_PI_A0_STATE], u8g_pgm_read(ptr));
//u8g->pin_list[U8G_PI_A0_STATE] = 2;
ptr++;
arg_val--;
}
}
break;
}
return 1;
}
uint8_t u8g_com_atmega_parallel_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
{
switch(msg)
{
case U8G_COM_MSG_INIT:
/* setup the RW pin as output and force it to low */
u8g_SetPIOutput(u8g, U8G_PI_RW);
u8g_SetPILevel(u8g, U8G_PI_RW, 0);
u8g_SetPIOutput(u8g, U8G_PI_D0);
u8g_SetPIOutput(u8g, U8G_PI_D1);
u8g_SetPIOutput(u8g, U8G_PI_D2);
u8g_SetPIOutput(u8g, U8G_PI_D3);
u8g_SetPIOutput(u8g, U8G_PI_D4);
u8g_SetPIOutput(u8g, U8G_PI_D5);
u8g_SetPIOutput(u8g, U8G_PI_D6);
u8g_SetPIOutput(u8g, U8G_PI_D7);
u8g_SetPIOutput(u8g, U8G_PI_EN);
u8g_SetPIOutput(u8g, U8G_PI_CS1);
u8g_SetPIOutput(u8g, U8G_PI_CS2);
u8g_SetPIOutput(u8g, U8G_PI_DI);
u8g_SetPILevel(u8g, U8G_PI_CS1, 1);
u8g_SetPILevel(u8g, U8G_PI_CS2, 1);
break;
case U8G_COM_MSG_STOP:
break;
case U8G_COM_MSG_CHIP_SELECT:
if ( arg_val == 0 )
{
/* disable */
u8g_SetPILevel(u8g, U8G_PI_CS1, 1);
u8g_SetPILevel(u8g, U8G_PI_CS2, 1);
}
else if ( arg_val == 1 )
{
/* enable */
u8g_SetPILevel(u8g, U8G_PI_CS1, 0);
u8g_SetPILevel(u8g, U8G_PI_CS2, 1);
}
else if ( arg_val == 2 )
{
/* enable */
u8g_SetPILevel(u8g, U8G_PI_CS1, 1);
u8g_SetPILevel(u8g, U8G_PI_CS2, 0);
}
else
{
/* enable */
u8g_SetPILevel(u8g, U8G_PI_CS1, 0);
u8g_SetPILevel(u8g, U8G_PI_CS2, 0);
}
break;
case U8G_COM_MSG_WRITE_BYTE:
u8g_com_atmega_parallel_write(u8g, arg_val);
break;
case U8G_COM_MSG_WRITE_SEQ:
{
register uint8_t *ptr = arg_ptr;
while( arg_val > 0 )
{
u8g_com_atmega_parallel_write(u8g, *ptr++);
arg_val--;
}
}
break;
case U8G_COM_MSG_WRITE_SEQ_P:
{
register uint8_t *ptr = arg_ptr;
while( arg_val > 0 )
{
u8g_com_atmega_parallel_write(u8g, u8g_pgm_read(ptr));
ptr++;
arg_val--;
}
}
break;
case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
u8g_SetPILevel(u8g, U8G_PI_DI, arg_val);
break;
}
return 1;
}
