/* Level 1 Block, 1GB, entry in LPAE Descriptor format for the given physical address */
lpaed_t hvmm_mm_lpaed_l1_block( uint64_t pa, uint8_t attr_idx )
{
/* lpae.c */
lpaed_t lpaed;
printh( "[mm] hvmm_mm_lpaed_l1_block:\n\r" );
printh( " pa:"); uart_print_hex64(pa); printh("\n\r");
printh( " attr_idx:"); uart_print_hex32((uint32_t) attr_idx); printh("\n\r");
// Valid Block Entry
lpaed.pt.valid = 1;
lpaed.pt.table = 0;
lpaed.bits &= ~TTBL_L1_OUTADDR_MASK;
lpaed.bits |= pa & TTBL_L1_OUTADDR_MASK;
lpaed.pt.sbz = 0;
// Lower block attributes
lpaed.pt.ai = attr_idx;
lpaed.pt.ns = 1; // Allow Non-secure access
lpaed.pt.user = 1;
lpaed.pt.ro = 0;
lpaed.pt.sh = 2; // Outher Shareable
lpaed.pt.af = 1; // Access Flag set to 1?
lpaed.pt.ng = 1;
// Upper block attributes
lpaed.pt.hint = 0;
lpaed.pt.pxn = 0;
lpaed.pt.xn = 0; // eXecute Never = 0
return lpaed;
}
void scheduler_test_switch_to_next_guest(void *pdata){
struct arch_regs *regs = pdata;
uint64_t pct = read_cntpct();
uint32_t tval = read_cnthp_tval();
uart_print( "cntpct:"); uart_print_hex64(pct); uart_print("\n\r");
uart_print( "cnth_tval:"); uart_print_hex32(tval); uart_print("\n\r");
/* Note: As of context_switchto() and context_perform_switch() are available,
no need to test if trapped from Hyp mode.
context_perform_switch() takes care of it
*/
/* Test guest context switch */
if ( (regs->cpsr & 0x1F) != 0x1A ) {
scheduler_schedule();
}
}
static void test_start_timer(void)
{
uint32_t ctl;
uint32_t tval;
uint64_t pct;
HVMM_TRACE_ENTER();
/* every second */
tval = read_cntfrq();
write_cntp_tval(tval);
pct = read_cntpct();
uart_print("cntpct:");
uart_print_hex64(pct);
uart_print("\n\r");
uart_print("cntp_tval:");
uart_print_hex32(tval);
uart_print("\n\r");
/* enable timer */
ctl = read_cntp_ctl();
ctl |= 0x1;
write_cntp_ctl(ctl);
HVMM_TRACE_EXIT();
}
