static int
s3c2410_bus_receive(struct uart_softc *sc)
{
uart_rx_put(sc, uart_getreg(&sc->sc_bas, SSCOM_URXH));
return (0);
}
static int
msm_bus_receive(struct uart_softc *sc)
{
struct msm_uart_softc *u = (struct msm_uart_softc *)sc;
struct uart_bas *bas;
int c;
bas = &sc->sc_bas;
uart_lock(sc->sc_hwmtx);
/* Initialize Receive Path and interrupt */
SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);
SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_ENABLE);
u->ier |= UART_DM_RXLEV;
SETREG(bas, UART_DM_IMR, u->ier);
/* Loop over until we are full, or no data is available */
while (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) {
if (uart_rx_full(sc)) {
/* No space left in input buffer */
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
break;
}
/* Read RX FIFO */
c = uart_getreg(bas, UART_DM_RF(0));
uart_barrier(bas);
uart_rx_put(sc, c);
}
uart_unlock(sc->sc_hwmtx);
return (0);
}
static int
exynos4210_bus_receive(struct uart_softc *sc)
{
struct uart_bas *bas;
bas = &sc->sc_bas;
while (bus_space_read_4(bas->bst, bas->bsh,
SSCOM_UFSTAT) & UFSTAT_RXCOUNT)
uart_rx_put(sc, uart_getreg(&sc->sc_bas, SSCOM_URXH));
return (0);
}
static int
sa1110_bus_receive(struct uart_softc *sc)
{
#if 0
while (!(uart_getreg(&sc->sc_bas, SACOM_SR1) & SR1_RNE)) {
u_int32_t sr0;
sr0 = uart_getreg(&sc->sc_bas, SACOM_SR0);
if (ISSET(sr0, SR0_RBB))
uart_setreg(&sc->sc_bas, SACOM_SR0, SR0_RBB);
if (ISSET(sr0, SR0_REB))
uart_setreg(&sc->sc_bas, SACOM_SR0, SR0_REB);
}
#endif
uart_setreg(&sc->sc_bas, SACOM_CR3, uart_getreg(&sc->sc_bas, SACOM_CR3)
| CR3_RIE);
uart_rx_put(sc, uart_getreg(&sc->sc_bas, SACOM_DR));
return (0);
}
