// Receive data into module
void main_vendor_bulk_in_received(udd_ep_status_t status, iram_size_t nb_transfered) {
if (status != UDD_EP_TRANSFER_OK) {
return; // Transfer aborted, then stop loopback
}
udi_vendor_bulk_out_run(&usbRx, sizeof(usbRx), main_vendor_read_callback);
}
void main_vendor_bulk_out_received(udd_ep_status_t status,
iram_size_t nb_transfered, udd_ep_id_t ep)
{
UNUSED(ep);
if (UDD_EP_TRANSFER_OK != status) {
// Transfer aborted
//restart
udi_vendor_bulk_out_run(
main_buf_loopback,
sizeof(main_buf_loopback),
main_vendor_bulk_out_received);
return;
}
if (blockendpoint_usage == bep_emem){
for(unsigned int i = 0; i < nb_transfered; i++){
xram[i] = main_buf_loopback[i];
}
if (FPGA_lockstatus() == fpga_blockout){
FPGA_setlock(fpga_unlocked);
}
} else if (blockendpoint_usage == bep_fpgabitstream){
/* Send byte to FPGA - this could eventually be done via SPI */
for(unsigned int i = 0; i < nb_transfered; i++){
fpga_program_sendbyte(main_buf_loopback[i]);
}
FPGA_CCLK_LOW();
}
//printf("BULKOUT: %d bytes\n", (int)nb_transfered);
udi_vendor_bulk_out_run(
main_buf_loopback,
sizeof(main_buf_loopback),
main_vendor_bulk_out_received);
}
bool main_vendor_enable(void)
{
main_b_vendor_enable = true;
// Start data reception on OUT endpoints
#if UDI_VENDOR_EPS_SIZE_BULK_FS
//main_vendor_bulk_in_received(UDD_EP_TRANSFER_OK, 0, 0);
udi_vendor_bulk_out_run(
main_buf_loopback,
sizeof(main_buf_loopback),
main_vendor_bulk_out_received);
#endif
return true;
}
void main_vendor_bulk_in_received(udd_ep_status_t status,
iram_size_t nb_transfered, udd_ep_id_t ep)
{
UNUSED(nb_transfered);
UNUSED(ep);
if (UDD_EP_TRANSFER_OK != status) {
return; // Transfer aborted, then stop loopback
}
ui_loop_back_state(false);
// Wait a full buffer
udi_vendor_bulk_out_run(
main_buf_loopback,
sizeof(main_buf_loopback),
main_vendor_bulk_out_received);
}
