/**
* @brief Configures and activates the SPI peripheral.
*
* @param[in] spip pointer to the @p SPIDriver object
*
* @notapi
*/
void spi_lld_start(SPIDriver *spip)
{
if (spip->state == SPI_STOP) {
/* Clock activation.*/
#if TIVA_SPI_USE_SSI0
if (&SPID1 == spip) {
bool b;
b = udmaChannelAllocate(spip->dmarxnr);
osalDbgAssert(!b, "channel already allocated");
b = udmaChannelAllocate(spip->dmatxnr);
osalDbgAssert(!b, "channel already allocated");
/* Enable SSI0 module.*/
SYSCTL->RCGCSSI |= (1 << 0);
while (!(SYSCTL->PRSSI & (1 << 0)))
;
nvicEnableVector(TIVA_SSI0_NUMBER, TIVA_SPI_SSI0_IRQ_PRIORITY);
}
#endif
#if TIVA_SPI_USE_SSI1
if (&SPID2 == spip) {
bool b;
b = udmaChannelAllocate(spip->dmarxnr);
osalDbgAssert(!b, "channel already allocated");
b = udmaChannelAllocate(spip->dmatxnr);
osalDbgAssert(!b, "channel already allocated");
/* Enable SSI0 module.*/
SYSCTL->RCGCSSI |= (1 << 1);
while (!(SYSCTL->PRSSI & (1 << 1)))
;
nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY);
}
#endif
#if TIVASPI_USE_SSI2
if (&SPID2 == spip) {
bool b;
b = udmaChannelAllocate(spip->dmarxnr);
osalDbgAssert(!b, "channel already allocated");
b = udmaChannelAllocate(spip->dmatxnr);
osalDbgAssert(!b, "channel already allocated");
/* Enable SSI0 module.*/
SYSCTL->RCGCSSI |= (1 << 2);
while (!(SYSCTL->PRSSI & (1 << 2)))
;
nvicEnableVector(TIVA_SSI2_NUMBER, TIVA_SPI_SSI2_IRQ_PRIORITY);
}
#endif
#if TIVA_SPI_USE_SSI3
if (&SPID2 == spip) {
bool b;
b = udmaChannelAllocate(spip->dmarxnr);
osalDbgAssert(!b, "channel already allocated");
b = udmaChannelAllocate(spip->dmatxnr);
osalDbgAssert(!b, "channel already allocated");
/* Enable SSI0 module.*/
SYSCTL->RCGCSSI |= (1 << 3);
while (!(SYSCTL->PRSSI & (1 << 3)))
;
nvicEnableVector(TIVA_SSI3_NUMBER, TIVA_SPI_SSI3_IRQ_PRIORITY);
}
#endif
UDMA->CHMAP[spip->dmarxnr / 8] |= (spip->rxchnmap << (spip->dmarxnr % 8));
UDMA->CHMAP[spip->dmatxnr / 8] |= (spip->txchnmap << (spip->dmatxnr % 8));
}
/* Set master operation mode.*/
spip->ssi->CR1 = 0;
/* Clock configuration - System Clock.*/
spip->ssi->CC = 0;
/* Clear pending interrupts.*/
spip->ssi->ICR = TIVA_ICR_RTIC | TIVA_ICR_RORIC;
/* Enable Receive Time-Out and Receive Overrun Interrupts.*/
spip->ssi->IM = TIVA_IM_RTIM | TIVA_IM_RORIM;
/* Configure the clock prescale divisor.*/
spip->ssi->CPSR = spip->config->cpsr;
/* Serial clock rate, phase/polarity, data size, fixed SPI frame format.*/
spip->ssi->CR0 = (spip->config->cr0 & ~TIVA_CR0_FRF_MASK) | TIVA_CR0_FRF(0);
/* Enable SSI.*/
spip->ssi->CR1 |= TIVA_CR1_SSE;
/* Enable RX and TX DMA channels.*/
spip->ssi->DMACTL = (TIVA_DMACTL_TXDMAE | TIVA_DMACTL_RXDMAE);
}
/**
* @brief Configures and activates the UART peripheral.
*
* @param[in] uartp pointer to the @p UARTDriver object
*
* @notapi
*/
void uart_lld_start(UARTDriver *uartp) {
if (uartp->state == UART_STOP) {
#if TIVA_UART_USE_UART0
if (&UARTD1 == uartp) {
bool b;
b = udmaChannelAllocate(uartp->dmarxnr);
osalDbgAssert(!b, "channel already allocated");
b = udmaChannelAllocate(uartp->dmatxnr);
osalDbgAssert(!b, "channel already allocated");
HWREG(SYSCTL_RCGCUART) |= (1 << 0);
while (!(HWREG(SYSCTL_PRUART) & (1 << 0)))
;
nvicEnableVector(TIVA_UART0_NUMBER, TIVA_UART_UART0_PRIORITY);
}
#endif
#if TIVA_UART_USE_UART1
if (&UARTD2 == uartp) {
bool b;
b = udmaChannelAllocate(uartp->dmarxnr);
osalDbgAssert(!b, "channel already allocated");
b = udmaChannelAllocate(uartp->dmatxnr);
osalDbgAssert(!b, "channel already allocated");
HWREG(SYSCTL_RCGCUART) |= (1 << 1);
while (!(HWREG(SYSCTL_PRUART) & (1 << 1)))
;
nvicEnableVector(TIVA_UART1_NUMBER, TIVA_UART_UART1_PRIORITY);
}
#endif
#if TIVA_UART_USE_UART2
if (&UARTD3 == uartp) {
bool b;
b = udmaChannelAllocate(uartp->dmarxnr);
osalDbgAssert(!b, "channel already allocated");
b = udmaChannelAllocate(uartp->dmatxnr);
osalDbgAssert(!b, "channel already allocated");
HWREG(SYSCTL_RCGCUART) |= (1 << 2);
while (!(HWREG(SYSCTL_PRUART) & (1 << 2)))
;
nvicEnableVector(TIVA_UART2_NUMBER, TIVA_UART_UART2_PRIORITY);
}
#endif
#if TIVA_UART_USE_UART3
if (&UARTD4 == uartp) {
bool b;
b = udmaChannelAllocate(uartp->dmarxnr);
osalDbgAssert(!b, "channel already allocated");
b = udmaChannelAllocate(uartp->dmatxnr);
osalDbgAssert(!b, "channel already allocated");
HWREG(SYSCTL_RCGCUART) |= (1 << 3);
while (!(HWREG(SYSCTL_PRUART) & (1 << 3)))
;
nvicEnableVector(TIVA_UART3_NUMBER, TIVA_UART_UART3_PRIORITY);
}
#endif
#if TIVA_UART_USE_UART4
if (&UARTD5 == uartp) {
bool b;
b = udmaChannelAllocate(uartp->dmarxnr);
osalDbgAssert(!b, "channel already allocated");
b = udmaChannelAllocate(uartp->dmatxnr);
osalDbgAssert(!b, "channel already allocated");
HWREG(SYSCTL_RCGCUART) |= (1 << 4);
while (!(HWREG(SYSCTL_PRUART) & (1 << 4)))
;
nvicEnableVector(TIVA_UART4_NUMBER, TIVA_UART_UART4_PRIORITY);
}
#endif
#if TIVA_UART_USE_UART5
if (&UARTD6 == uartp) {
bool b;
b = udmaChannelAllocate(uartp->dmarxnr);
osalDbgAssert(!b, "channel already allocated");
b = udmaChannelAllocate(uartp->dmatxnr);
osalDbgAssert(!b, "channel already allocated");
HWREG(SYSCTL_RCGCUART) |= (1 << 5);
while (!(HWREG(SYSCTL_PRUART) & (1 << 5)))
;
nvicEnableVector(TIVA_UART5_NUMBER, TIVA_UART_UART5_PRIORITY);
}
#endif
#if TIVA_UART_USE_UART6
if (&UARTD7 == uartp) {
bool b;
b = udmaChannelAllocate(uartp->dmarxnr);
osalDbgAssert(!b, "channel already allocated");
b = udmaChannelAllocate(uartp->dmatxnr);
osalDbgAssert(!b, "channel already allocated");
HWREG(SYSCTL_RCGCUART) |= (1 << 6);
while (!(HWREG(SYSCTL_PRUART) & (1 << 6)))
;
nvicEnableVector(TIVA_UART6_NUMBER, TIVA_UART_UART6_PRIORITY);
}
#endif
#if TIVA_UART_USE_UART7
if (&UARTD8 == uartp) {
bool b;
b = udmaChannelAllocate(uartp->dmarxnr);
osalDbgAssert(!b, "channel already allocated");
b = udmaChannelAllocate(uartp->dmatxnr);
osalDbgAssert(!b, "channel already allocated");
HWREG(SYSCTL_RCGCUART) |= (1 << 7);
while (!(HWREG(SYSCTL_PRUART) & (1 << 7)))
;
nvicEnableVector(TIVA_UART7_NUMBER, TIVA_UART_UART7_PRIORITY);
}
#endif
uartp->rxbuf = 0;
HWREG(UDMA_CHMAP0 + (uartp->dmarxnr / 8) * 4) |= (uartp->rxchnmap << (uartp->dmarxnr % 8));
HWREG(UDMA_CHMAP0 + (uartp->dmatxnr / 8) * 4) |= (uartp->txchnmap << (uartp->dmatxnr % 8));
}
uartp->rxstate = UART_RX_IDLE;
uartp->txstate = UART_TX_IDLE;
uart_init(uartp);
}