/* configuration has to be done through the TSEC1 MIIM regs */ int read_phy_reg (struct eth_device *dev, int mii_id, int regnum) { uec_private_t *ugeth = (uec_private_t *) dev->priv; uec_t *ug_regs; enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; u32 tmp_reg; u16 value; ug_regs = ugeth->uec_regs; /* Setting up the MII Mangement Address Register */ tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; out_be32 (&ug_regs->miimadd, tmp_reg); /* Perform an MII management read cycle */ out_be32 (&ug_regs->miimcom, 0); out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE); /* Wait till MII management write is complete */ while ((in_be32 (&ug_regs->miimind)) & (MIIMIND_NOT_VALID | MIIMIND_BUSY)); udelay (100000); /* Read MII management status */ value = (u16) in_be32 (&ug_regs->miimstat); if (value == 0xffff) ugphy_warn ("read wrong value : mii_id %d,mii_reg %d, base %08x", mii_id, mii_reg, (u32) & (ug_regs->miimcfg)); return (value); }
/* configuration has to be done through the TSEC1 MIIM regs */ int read_phy_reg(struct net_device *dev, int mii_id, int regnum) { struct ucc_geth_private *ugeth = netdev_priv(dev); struct ucc_mii_mng *mii_regs; enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg) regnum; u32 tmp_reg; u16 value; ugphy_vdbg("%s: IN", __FUNCTION__); spin_lock_irq(&ugeth->lock); mii_regs = ugeth->mii_info->mii_regs; /* Setting up the MII Mangement Address Register */ tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; out_be32(&mii_regs->miimadd, tmp_reg); /* Perform an MII management read cycle */ out_be32(&mii_regs->miimcom, MIIMCOM_READ_CYCLE); /* Wait till MII management write is complete */ while ((in_be32(&mii_regs->miimind)) & MIIMIND_BUSY) cpu_relax(); udelay(10000); /* Read MII management status */ value = (u16) in_be32(&mii_regs->miimstat); out_be32(&mii_regs->miimcom, 0); if (value == 0xffff) ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x", mii_id, mii_reg, (u32) & (mii_regs->miimcfg)); spin_unlock_irq(&ugeth->lock); return (value); }