void mm1_state::machine_reset()
{
address_space *program = m_maincpu->memory().space(AS_PROGRAM);
int i;
/* reset LS259 */
for (i = 0; i < 8; i++) ls259_w(*program, i, 0);
/* set FDC ready */
if (!input_port_read(machine(), "T5")) upd765_ready_w(m_fdc, 1);
/* reset FDC */
upd765_reset_w(m_fdc, 1);
upd765_reset_w(m_fdc, 0);
}
void pc1512_state::set_fdc_dsr(UINT8 data)
{
/*
bit description
0 Drive Select Bit 0 (DS0)
1 Drive Select Bit 1 (DS1)
2 765A reset
3 Allow 765A FDC to interrupt and request DMA
4 Switch motor(s) on and enable drive 0 selection
5 Switch motor(s) on and enable drive 1 selection
6
7
*/
m_fdc_dsr = data;
m_nden = BIT(data, 3);
update_fdc_int();
update_fdc_drq();
update_fdc_tc();
upd765_reset_w(m_fdc, BIT(data, 2));
floppy_mon_w(m_floppy0, BIT(data, 4) ? CLEAR_LINE : ASSERT_LINE);
floppy_mon_w(m_floppy1, BIT(data, 5) ? CLEAR_LINE : ASSERT_LINE);
}
/*-------------------------------------------------------------------------*/
static void compis_fdc_reset(running_machine &machine)
{
device_t *fdc = machine.device("upd765");
upd765_reset(fdc, 0);
/* set FDC at reset */
upd765_reset_w(fdc, 1);
}
// RESET the disc2 Unit !
void hector_disc2_reset(running_machine &machine)
{
hec2hrp_state *state = machine.driver_data<hec2hrp_state>();
// Initialization Disc2 unit
cputag_set_input_line(machine, "disc2cpu" , INPUT_LINE_RESET, PULSE_LINE);
//switch ON and OFF the reset line uPD
upd765_reset_w(machine.device("upd765"), 1);
upd765_reset_w(machine.device("upd765"), 0);
// Select ROM memory to cold restart
state->membank("bank3")->set_entry(DISCII_BANK_ROM);
// Clear the Hardware's buffers
state->m_hector_disc2_data_r_ready=0x0; /* =ff when PC2 = true and data in read buffer (state->m_hector_disc2_data_read) */
state->m_hector_disc2_data_w_ready=0x0; /* =ff when Disc 2 Port 40 had send a data in write buffer (state->m_hector_disc2_data_write) */
state->m_hector_disc2_data_read=0; /* Data send by Hector to Disc 2 when PC2=true */
state->m_hector_disc2_data_write=0; /* Data send by Disc 2 to Hector when Write Port I/O 40 */
state->m_hector_disc2_RNMI = 0; /* State of I/O 50 D5 = authorization for INT / NMI */
state->m_NMI_current_state=0; /* Clear the DMA active request */
}
static WRITE8_HANDLER(elwro800jr_fdc_control_w)
{
device_t *fdc = space->machine().device("upd765");
floppy_mon_w(floppy_get_device(space->machine(), 0), !BIT(data, 0));
floppy_mon_w(floppy_get_device(space->machine(), 1), !BIT(data, 1));
floppy_drive_set_ready_state(floppy_get_device(space->machine(), 0), 1,1);
floppy_drive_set_ready_state(floppy_get_device(space->machine(), 1), 1,1);
upd765_tc_w(fdc, data & 0x04);
upd765_reset_w(fdc, !(data & 0x08));
}
void pc_fdc_reset(running_machine &machine)
{
/* setup reset condition */
fdc->data_rate_register = 2;
fdc->digital_output_register = 0;
/* bit 7 is disk change */
fdc->digital_input_register = 0x07f;
upd765_reset(pc_get_device(machine),0);
/* set FDC at reset */
upd765_reset_w(pc_get_device(machine), 1);
}
