void AudioOutputI2S::begin(void)
{
dma.begin(true); // Allocate the DMA channel first
block_left_1st = NULL;
block_right_1st = NULL;
// TODO: should we set & clear the I2S_TCSR_SR bit here?
config_i2s();
CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
#if defined(KINETISK)
dma.TCD->SADDR = i2s_tx_buffer;
dma.TCD->SOFF = 2;
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
dma.TCD->NBYTES_MLNO = 2;
dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
dma.TCD->DADDR = (void *)((uint32_t)&I2S0_TDR0 + 2);
dma.TCD->DOFF = 0;
dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
dma.TCD->DLASTSGA = 0;
dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
#endif
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
update_responsibility = update_setup();
dma.enable();
I2S0_TCSR = I2S_TCSR_SR;
I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
dma.attachInterrupt(isr);
}
void AudioInputI2SQuad::begin(void)
{
dma.begin(true); // Allocate the DMA channel first
// TODO: should we set & clear the I2S_RCSR_SR bit here?
AudioOutputI2SQuad::config_i2s();
CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0
CORE_PIN30_CONFIG = PORT_PCR_MUX(4); // pin 30, PTC11, I2S0_RXD1
#if defined(KINETISK)
dma.TCD->SADDR = &I2S0_RDR0;
dma.TCD->SOFF = 4;
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_SMOD(3) | DMA_TCD_ATTR_DSIZE(1);
dma.TCD->NBYTES_MLNO = 4;
dma.TCD->SLAST = 0;
dma.TCD->DADDR = i2s_rx_buffer;
dma.TCD->DOFF = 2;
dma.TCD->CITER_ELINKNO = sizeof(i2s_rx_buffer) / 4;
dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 4;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
#endif
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX);
update_responsibility = update_setup();
dma.enable();
I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX
dma.attachInterrupt(isr);
}
void AudioOutputI2SQuad::begin(void)
{
#if 1
dma.begin(true); // Allocate the DMA channel first
block_ch1_1st = NULL;
block_ch2_1st = NULL;
block_ch3_1st = NULL;
block_ch4_1st = NULL;
// TODO: can we call normal config_i2s, and then just enable the extra output?
config_i2s();
CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 -> ch1 & ch2
CORE_PIN15_CONFIG = PORT_PCR_MUX(6); // pin 15, PTC0, I2S0_TXD1 -> ch3 & ch4
dma.TCD->SADDR = i2s_tx_buffer;
dma.TCD->SOFF = 2;
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1) | DMA_TCD_ATTR_DMOD(3);
dma.TCD->NBYTES_MLNO = 4;
dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
dma.TCD->DADDR = &I2S0_TDR0;
dma.TCD->DOFF = 4;
dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 4;
dma.TCD->DLASTSGA = 0;
dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 4;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
update_responsibility = update_setup();
dma.enable();
I2S0_TCSR = I2S_TCSR_SR;
I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
dma.attachInterrupt(isr);
#endif
}
void AudioOutputI2S2::begin(void)
{
dma.begin(true); // Allocate the DMA channel first
block_left_1st = NULL;
block_right_1st = NULL;
config_i2s();
CORE_PIN2_CONFIG = 2; //2:TX_DATA0
dma.TCD->SADDR = i2s2_tx_buffer;
dma.TCD->SOFF = 2;
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
dma.TCD->NBYTES_MLNO = 2;
dma.TCD->SLAST = -sizeof(i2s2_tx_buffer);
dma.TCD->DOFF = 0;
dma.TCD->CITER_ELINKNO = sizeof(i2s2_tx_buffer) / 2;
dma.TCD->DLASTSGA = 0;
dma.TCD->BITER_ELINKNO = sizeof(i2s2_tx_buffer) / 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
dma.TCD->DADDR = (void *)((uint32_t)&I2S2_TDR0 + 2);
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_TX);
// I2S2_RCSR |= I2S_RCSR_RE;
I2S2_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
update_responsibility = update_setup();
dma.attachInterrupt(isr);
dma.enable();
}
void AudioOutputI2S2slave::begin(void)
{
dma.begin(true); // Allocate the DMA channel first
//pinMode(2, OUTPUT);
block_left_1st = NULL;
block_right_1st = NULL;
AudioOutputI2S2slave::config_i2s();
CORE_PIN2_CONFIG = 2; //2:TX_DATA0
//CORE_PIN33_CONFIG = 2; //2:RX_DATA0
dma.TCD->SADDR = i2s2_tx_buffer;
dma.TCD->SOFF = 2;
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
dma.TCD->NBYTES_MLNO = 2;
dma.TCD->SLAST = -sizeof(i2s2_tx_buffer);
dma.TCD->DADDR = (void *)((uint32_t)&I2S2_TDR0 + 2);
dma.TCD->DOFF = 0;
dma.TCD->CITER_ELINKNO = sizeof(i2s2_tx_buffer) / 2;
dma.TCD->DLASTSGA = 0;
dma.TCD->BITER_ELINKNO = sizeof(i2s2_tx_buffer) / 2;
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_TX);
update_responsibility = update_setup();
dma.enable();
dma.attachInterrupt(isr);
}
void AudioInputTDM2::begin(void)
{
dma.begin(true); // Allocate the DMA channel first
// TODO: should we set & clear the I2S_RCSR_SR bit here?
AudioOutputTDM2::config_tdm();
CORE_PIN33_CONFIG = 2; //2:RX_DATA0
IOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 0;
dma.TCD->SADDR = &I2S2_RDR0;
dma.TCD->SOFF = 0;
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(2) | DMA_TCD_ATTR_DSIZE(2);
dma.TCD->NBYTES_MLNO = 4;
dma.TCD->SLAST = 0;
dma.TCD->DADDR = tdm_rx_buffer;
dma.TCD->DOFF = 4;
dma.TCD->CITER_ELINKNO = sizeof(tdm_rx_buffer) / 4;
dma.TCD->DLASTSGA = -sizeof(tdm_rx_buffer);
dma.TCD->BITER_ELINKNO = sizeof(tdm_rx_buffer) / 4;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI2_RX);
update_responsibility = update_setup();
dma.enable();
I2S2_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
I2S2_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE;
dma.attachInterrupt(isr);
}
void AudioOutputAnalog::begin(void)
{
dma.begin(true); // Allocate the DMA channel first
SIM_SCGC2 |= SIM_SCGC2_DAC0;
DAC0_C0 = DAC_C0_DACEN; // 1.2V VDDA is DACREF_2
// slowly ramp up to DC voltage, approx 1/4 second
for (int16_t i=0; i<2048; i+=8) {
*(int16_t *)&(DAC0_DAT0L) = i;
delay(1);
}
// set the programmable delay block to trigger DMA requests
if (!(SIM_SCGC6 & SIM_SCGC6_PDB)
|| (PDB0_SC & PDB_CONFIG) != PDB_CONFIG
|| PDB0_MOD != PDB_PERIOD
|| PDB0_IDLY != 1
|| PDB0_CH0C1 != 0x0101) {
SIM_SCGC6 |= SIM_SCGC6_PDB;
PDB0_IDLY = 1;
PDB0_MOD = PDB_PERIOD;
PDB0_SC = PDB_CONFIG | PDB_SC_LDOK;
PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG;
PDB0_CH0C1 = 0x0101;
}
dma.TCD->SADDR = dac_buffer;
dma.TCD->SOFF = 2;
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
dma.TCD->NBYTES_MLNO = 2;
dma.TCD->SLAST = -sizeof(dac_buffer);
dma.TCD->DADDR = &DAC0_DAT0L;
dma.TCD->DOFF = 0;
dma.TCD->CITER_ELINKNO = sizeof(dac_buffer) / 2;
dma.TCD->DLASTSGA = 0;
dma.TCD->BITER_ELINKNO = sizeof(dac_buffer) / 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_PDB);
update_responsibility = update_setup();
dma.enable();
dma.attachInterrupt(isr);
}
void AudioInputI2S::begin(void)
{
//block_left_1st = NULL;
//block_right_1st = NULL;
//pinMode(3, OUTPUT);
//digitalWriteFast(3, HIGH);
//delayMicroseconds(500);
//digitalWriteFast(3, LOW);
// TODO: should we set & clear the I2S_RCSR_SR bit here?
AudioOutputI2S::config_i2s();
CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0
DMA_CR = 0;
DMA_TCD1_SADDR = &I2S0_RDR0;
DMA_TCD1_SOFF = 0;
DMA_TCD1_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
DMA_TCD1_NBYTES_MLNO = 2;
DMA_TCD1_SLAST = 0;
DMA_TCD1_DADDR = i2s_rx_buffer;
DMA_TCD1_DOFF = 2;
DMA_TCD1_CITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
DMA_TCD1_DLASTSGA = -sizeof(i2s_rx_buffer);
DMA_TCD1_BITER_ELINKNO = sizeof(i2s_rx_buffer) / 2;
DMA_TCD1_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
DMAMUX0_CHCFG1 = DMAMUX_DISABLE;
DMAMUX0_CHCFG1 = DMAMUX_SOURCE_I2S0_RX | DMAMUX_ENABLE;
update_responsibility = update_setup();
DMA_SERQ = 1;
// TODO: is I2S_RCSR_BCE appropriate if sync'd to transmitter clock?
//I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_FRDE | I2S_RCSR_FR;
NVIC_ENABLE_IRQ(IRQ_DMA_CH1);
}
void AudioInputAnalogStereo::init(uint8_t pin0, uint8_t pin1)
{
uint32_t i, sum0=0, sum1=0;
//pinMode(32, OUTPUT);
//pinMode(33, OUTPUT);
// Configure the ADC and run at least one software-triggered
// conversion. This completes the self calibration stuff and
// leaves the ADC in a state that's mostly ready to use
analogReadRes(16);
analogReference(INTERNAL); // range 0 to 1.2 volts
#if F_BUS == 96000000 || F_BUS == 48000000 || F_BUS == 24000000
analogReadAveraging(8);
ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(1);
#else
analogReadAveraging(4);
ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(0);
#endif
// Actually, do many normal reads, to start with a nice DC level
for (i=0; i < 1024; i++) {
sum0 += analogRead(pin0);
sum1 += analogReadADC1(pin1);
}
for (i = 0; i < 16; i++) {
left_dc_average_hist[i] = sum0 >> 10;
right_dc_average_hist[i] = sum1 >> 10;
}
// set the programmable delay block to trigger the ADC at 44.1 kHz
//if (!(SIM_SCGC6 & SIM_SCGC6_PDB)
//|| (PDB0_SC & PDB_CONFIG) != PDB_CONFIG
//|| PDB0_MOD != PDB_PERIOD
//|| PDB0_IDLY != 1
//|| PDB0_CH0C1 != 0x0101) {
SIM_SCGC6 |= SIM_SCGC6_PDB;
PDB0_IDLY = 1;
PDB0_MOD = PDB_PERIOD;
PDB0_SC = PDB_CONFIG | PDB_SC_LDOK;
PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG;
PDB0_CH0C1 = 0x0101;
PDB0_CH1C1 = 0x0101;
//}
// enable the ADC for hardware trigger and DMA
ADC0_SC2 |= ADC_SC2_ADTRG | ADC_SC2_DMAEN;
ADC1_SC2 |= ADC_SC2_ADTRG | ADC_SC2_DMAEN;
// set up a DMA channel to store the ADC data
dma0.begin(true);
dma1.begin(true);
// ADC0_RA = 0x4003B010
// ADC1_RA = 0x400BB010
dma0.TCD->SADDR = &ADC0_RA;
dma0.TCD->SOFF = 0;
dma0.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
dma0.TCD->NBYTES_MLNO = 2;
dma0.TCD->SLAST = 0;
dma0.TCD->DADDR = left_buffer;
dma0.TCD->DOFF = 2;
dma0.TCD->CITER_ELINKNO = sizeof(left_buffer) / 2;
dma0.TCD->DLASTSGA = -sizeof(left_buffer);
dma0.TCD->BITER_ELINKNO = sizeof(left_buffer) / 2;
dma0.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
dma1.TCD->SADDR = &ADC1_RA;
dma1.TCD->SOFF = 0;
dma1.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
dma1.TCD->NBYTES_MLNO = 2;
dma1.TCD->SLAST = 0;
dma1.TCD->DADDR = right_buffer;
dma1.TCD->DOFF = 2;
dma1.TCD->CITER_ELINKNO = sizeof(right_buffer) / 2;
dma1.TCD->DLASTSGA = -sizeof(right_buffer);
dma1.TCD->BITER_ELINKNO = sizeof(right_buffer) / 2;
dma1.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
dma0.triggerAtHardwareEvent(DMAMUX_SOURCE_ADC0);
//dma1.triggerAtHardwareEvent(DMAMUX_SOURCE_ADC1);
dma1.triggerAtTransfersOf(dma0);
dma1.triggerAtCompletionOf(dma0);
update_responsibility = update_setup();
dma0.enable();
dma1.enable();
dma0.attachInterrupt(isr0);
dma1.attachInterrupt(isr1);
}
void AudioInputAnalog::begin(unsigned int pin)
{
uint32_t i, sum=0;
// pin must be 0 to 13 (for A0 to A13)
// or 14 to 23 for digital pin numbers A0-A9
// or 34 to 37 corresponding to A10-A13
if (pin > 23 && !(pin >= 34 && pin <= 37)) return;
//pinMode(2, OUTPUT);
//pinMode(3, OUTPUT);
//digitalWriteFast(3, HIGH);
//delayMicroseconds(500);
//digitalWriteFast(3, LOW);
// Configure the ADC and run at least one software-triggered
// conversion. This completes the self calibration stuff and
// leaves the ADC in a state that's mostly ready to use
analogReadRes(16);
analogReference(INTERNAL); // range 0 to 1.2 volts
//analogReference(DEFAULT); // range 0 to 3.3 volts
analogReadAveraging(8);
// Actually, do many normal reads, to start with a nice DC level
for (i=0; i < 1024; i++) {
sum += analogRead(pin);
}
dc_average = sum >> 10;
// testing only, enable adc interrupt
//ADC0_SC1A |= ADC_SC1_AIEN;
//while ((ADC0_SC1A & ADC_SC1_COCO) == 0) ; // wait
//NVIC_ENABLE_IRQ(IRQ_ADC0);
// set the programmable delay block to trigger the ADC at 44.1 kHz
SIM_SCGC6 |= SIM_SCGC6_PDB;
PDB0_MOD = PDB_PERIOD;
PDB0_SC = PDB_CONFIG | PDB_SC_LDOK;
PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG;
PDB0_CH0C1 = 0x0101;
// enable the ADC for hardware trigger and DMA
ADC0_SC2 |= ADC_SC2_ADTRG | ADC_SC2_DMAEN;
// set up a DMA channel to store the ADC data
SIM_SCGC7 |= SIM_SCGC7_DMA;
SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
DMA_CR = 0;
DMA_TCD2_SADDR = &ADC0_RA;
DMA_TCD2_SOFF = 0;
DMA_TCD2_ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
DMA_TCD2_NBYTES_MLNO = 2;
DMA_TCD2_SLAST = 0;
DMA_TCD2_DADDR = analog_rx_buffer;
DMA_TCD2_DOFF = 2;
DMA_TCD2_CITER_ELINKNO = sizeof(analog_rx_buffer) / 2;
DMA_TCD2_DLASTSGA = -sizeof(analog_rx_buffer);
DMA_TCD2_BITER_ELINKNO = sizeof(analog_rx_buffer) / 2;
DMA_TCD2_CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
DMAMUX0_CHCFG2 = DMAMUX_DISABLE;
DMAMUX0_CHCFG2 = DMAMUX_SOURCE_ADC0 | DMAMUX_ENABLE;
update_responsibility = update_setup();
DMA_SERQ = 2;
NVIC_ENABLE_IRQ(IRQ_DMA_CH2);
}
void AudioInputAnalogStereo::init(uint8_t pin0, uint8_t pin1)
{
uint32_t tmp;
//pinMode(32, OUTPUT);
//pinMode(33, OUTPUT);
// Configure the ADC and run at least one software-triggered
// conversion. This completes the self calibration stuff and
// leaves the ADC in a state that's mostly ready to use
analogReadRes(16);
analogReference(INTERNAL); // range 0 to 1.2 volts
#if F_BUS == 96000000 || F_BUS == 48000000 || F_BUS == 24000000
analogReadAveraging(8);
ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(1);
#else
analogReadAveraging(4);
ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(0);
#endif
// Note for review:
// Probably not useful to spin cycles here stabilizing
// since DC blocking is similar to te external analog filters
tmp = (uint16_t) analogRead(pin0);
tmp = ( ((int32_t) tmp) << 14);
hpf_x1[0] = tmp; // With constant DC level x1 would be x0
hpf_y1[0] = 0; // Output will settle here when stable
tmp = (uint16_t) analogReadADC1(pin1);
tmp = ( ((int32_t) tmp) << 14);
hpf_x1[1] = tmp; // With constant DC level x1 would be x0
hpf_y1[1] = 0; // Output will settle here when stable
// set the programmable delay block to trigger the ADC at 44.1 kHz
//if (!(SIM_SCGC6 & SIM_SCGC6_PDB)
//|| (PDB0_SC & PDB_CONFIG) != PDB_CONFIG
//|| PDB0_MOD != PDB_PERIOD
//|| PDB0_IDLY != 1
//|| PDB0_CH0C1 != 0x0101) {
SIM_SCGC6 |= SIM_SCGC6_PDB;
PDB0_IDLY = 1;
PDB0_MOD = PDB_PERIOD;
PDB0_SC = PDB_CONFIG | PDB_SC_LDOK;
PDB0_SC = PDB_CONFIG | PDB_SC_SWTRIG;
PDB0_CH0C1 = 0x0101;
PDB0_CH1C1 = 0x0101;
//}
// enable the ADC for hardware trigger and DMA
ADC0_SC2 |= ADC_SC2_ADTRG | ADC_SC2_DMAEN;
ADC1_SC2 |= ADC_SC2_ADTRG | ADC_SC2_DMAEN;
// set up a DMA channel to store the ADC data
dma0.begin(true);
dma1.begin(true);
// ADC0_RA = 0x4003B010
// ADC1_RA = 0x400BB010
dma0.TCD->SADDR = &ADC0_RA;
dma0.TCD->SOFF = 0;
dma0.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
dma0.TCD->NBYTES_MLNO = 2;
dma0.TCD->SLAST = 0;
dma0.TCD->DADDR = left_buffer;
dma0.TCD->DOFF = 2;
dma0.TCD->CITER_ELINKNO = sizeof(left_buffer) / 2;
dma0.TCD->DLASTSGA = -sizeof(left_buffer);
dma0.TCD->BITER_ELINKNO = sizeof(left_buffer) / 2;
dma0.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
dma1.TCD->SADDR = &ADC1_RA;
dma1.TCD->SOFF = 0;
dma1.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
dma1.TCD->NBYTES_MLNO = 2;
dma1.TCD->SLAST = 0;
dma1.TCD->DADDR = right_buffer;
dma1.TCD->DOFF = 2;
dma1.TCD->CITER_ELINKNO = sizeof(right_buffer) / 2;
dma1.TCD->DLASTSGA = -sizeof(right_buffer);
dma1.TCD->BITER_ELINKNO = sizeof(right_buffer) / 2;
dma1.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
dma0.triggerAtHardwareEvent(DMAMUX_SOURCE_ADC0);
//dma1.triggerAtHardwareEvent(DMAMUX_SOURCE_ADC1);
dma1.triggerAtTransfersOf(dma0);
dma1.triggerAtCompletionOf(dma0);
update_responsibility = update_setup();
dma0.enable();
dma1.enable();
dma0.attachInterrupt(isr0);
dma1.attachInterrupt(isr1);
}