static uint32_t dsu_readIR(urj_chain_t *chain)
{
urj_tap_capture_ir(chain);
wir = urj_tap_register_fill(wir, 1);
urj_tap_shift_register(chain, wir, dsurir, URJ_CHAIN_EXITMODE_IDLE);
return urj_tap_register_get_value(dsurir);
}
static uint64_t dsu_readDR(urj_chain_t *chain, int size, uint64_t wdata)
{
urj_tap_register_t *rwr = urj_tap_register_alloc(size);
urj_tap_register_t *rrd = urj_tap_register_fill(urj_tap_register_alloc(size), 0);
uint64_t rdata;
urj_tap_register_set_value(rwr, wdata);
urj_tap_capture_dr(chain);
urj_tap_shift_register(chain, rwr, rrd, URJ_CHAIN_EXITMODE_IDLE);
rdata = urj_tap_register_get_value(rrd);
urj_tap_register_free(rwr);
urj_tap_register_free(rrd);
return rdata;
}
static void
nexus_access_set_addr (urj_bus_t *bus, uint32_t addr, int mode)
{
urj_tap_register_t *r = bus->part->active_instruction->data_register->in;
int i;
DBG (DBG_BASIC, _("%s: addr=%08lx, mode=%s\n"), __FUNCTION__,
(long unsigned) addr,
(mode == ACCESS_MODE_READ) ? "READ" : "WRITE");
urj_tap_register_fill (r, 0);
/* set address bits */
addr >>= 2;
for (i = 0; i < 7; i++)
register_set_bit (r, 27 + i, addr & (1 << i));
/* set access mode */
register_set_bit (r, 26, mode);
shift_data (bus, 32);
}
void dsu_init(void)
{
if (dsurir == NULL) dsurir = urj_tap_register_fill(urj_tap_register_alloc(DSU_IR_LEN), 0);
if (dsuwir == NULL) dsuwir = urj_tap_register_fill(urj_tap_register_alloc(DSU_IR_LEN), 0);
}
static uint32_t
ejtag_run_pracc (urj_bus_t *bus, const uint32_t *code, unsigned int len)
{
urj_data_register_t *ejaddr, *ejdata, *ejctrl;
int i, pass;
uint32_t addr, data, retval;
ejaddr = urj_part_find_data_register (bus->part, "EJADDRESS");
ejdata = urj_part_find_data_register (bus->part, "EJDATA");
ejctrl = urj_part_find_data_register (bus->part, "EJCONTROL");
if (!(ejaddr && ejdata && ejctrl))
{
urj_error_set (URJ_ERROR_NOTFOUND,
_("EJADDRESS, EJDATA or EJCONTROL register not found"));
return 0;
}
urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
urj_tap_chain_shift_instructions (bus->chain);
pass = 0;
retval = 0;
for (;;)
{
ejctrl->in->data[PrAcc] = 1;
urj_tap_chain_shift_data_registers (bus->chain, 0);
urj_tap_chain_shift_data_registers (bus->chain, 1);
urj_log (URJ_LOG_LEVEL_ALL, "ctrl=%s\n",
urj_tap_register_get_string (ejctrl->out));
if (ejctrl->out->data[Rocc])
{
urj_error_set (URJ_ERROR_BUS, _("Reset occurred, ctrl=%s"),
urj_tap_register_get_string (ejctrl->out));
bus->initialized = 0;
break;
}
if (!ejctrl->out->data[PrAcc])
{
urj_error_set (URJ_ERROR_BUS, _("No processor access, ctrl=%s"),
urj_tap_register_get_string (ejctrl->out));
bus->initialized = 0;
break;
}
urj_part_set_instruction (bus->part, "EJTAG_ADDRESS");
urj_tap_chain_shift_instructions (bus->chain);
urj_tap_chain_shift_data_registers (bus->chain, 1);
addr = reg_value (ejaddr->out);
if (addr & 3)
{
urj_error_set (URJ_ERROR_BUS,
_("PrAcc bad alignment: addr=0x%08lx"),
(long unsigned) addr);
addr &= ~3;
}
urj_part_set_instruction (bus->part, "EJTAG_DATA");
urj_tap_chain_shift_instructions (bus->chain);
urj_tap_register_fill (ejdata->in, 0);
if (ejctrl->out->data[PRnW])
{
urj_tap_chain_shift_data_registers (bus->chain, 1);
data = reg_value (ejdata->out);
urj_log (URJ_LOG_LEVEL_ALL,
_("%s(%d) PrAcc write: addr=0x%08lx data=0x%08lx\n"),
__FILE__, __LINE__,
(long unsigned) addr, (long unsigned) data);
if (addr == UINT32_C (0xff200000))
{
/* Return value from the target CPU. */
retval = data;
}
else
{
urj_error_set (URJ_ERROR_BUS,
_("Unknown write addr=0x%08lx data=0x%08lx"),
(long unsigned) addr, (long unsigned) data);
}
}
else
{
if (addr == UINT32_C (0xff200200) && pass++)
break;
data = 0;
if (addr >= 0xff200200 && addr < 0xff200200 + (len << 2))
{
data = code[(addr - 0xff200200) >> 2];
for (i = 0; i < 32; i++)
ejdata->in->data[i] = (data >> i) & 1;
}
urj_log (URJ_LOG_LEVEL_ALL,
"%s(%d) PrAcc read: addr=0x%08lx data=0x%08lx\n",
__FILE__, __LINE__,
(long unsigned) addr, (long unsigned) data);
urj_tap_chain_shift_data_registers (bus->chain, 0);
}
urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
urj_tap_chain_shift_instructions (bus->chain);
ejctrl->in->data[PrAcc] = 0;
urj_tap_chain_shift_data_registers (bus->chain, 0);
}
/**
* low level dma read operation
*
*/
static unsigned int
ejtag_dma_read (urj_bus_t *bus, unsigned int addr, int sz)
{
static urj_data_register_t *ejctrl = NULL;
static urj_data_register_t *ejaddr = NULL;
static urj_data_register_t *ejdata = NULL;
int i = 0;
int timeout = 5;
unsigned int ret;
if (ejctrl == NULL)
ejctrl = urj_part_find_data_register (bus->part, "EJCONTROL");
if (ejaddr == NULL)
ejaddr = urj_part_find_data_register (bus->part, "EJADDRESS");
if (ejdata == NULL)
ejdata = urj_part_find_data_register (bus->part, "EJDATA");
urj_part_set_instruction (bus->part, "EJTAG_ADDRESS");
urj_tap_chain_shift_instructions (bus->chain);
for (i = 0; i < 32; i++)
ejaddr->in->data[i] = (addr >> i) & 1;
urj_tap_chain_shift_data_registers (bus->chain, 0); /* Push the address to read */
urj_log (URJ_LOG_LEVEL_COMM, "Wrote to ejaddr->in =%s %08lX\n",
urj_tap_register_get_string (ejaddr->in),
(long unsigned) reg_value (ejaddr->in));
urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
urj_tap_chain_shift_instructions (bus->chain);
urj_tap_register_fill (ejctrl->in, 0);
ejctrl->in->data[PrAcc] = 1; // Processor access
ejctrl->in->data[ProbEn] = 1;
ejctrl->in->data[DmaAcc] = 1; // DMA operation request */
ejctrl->in->data[DstRt] = 1;
if (sz)
ejctrl->in->data[sz] = 1; // Size : can be WORD/HALFWORD or nothing for byte
ejctrl->in->data[DmaRwn] = 1; // This is a read
urj_tap_chain_shift_data_registers (bus->chain, 0); /* Do the operation */
urj_log (URJ_LOG_LEVEL_ALL, "Wrote to ejctrl->in =%s %08lX\n",
urj_tap_register_get_string (ejctrl->in),
(long unsigned) reg_value (ejctrl->in));
do
{
urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
urj_tap_chain_shift_instructions (bus->chain);
urj_tap_register_fill (ejctrl->in, 0);
ejctrl->in->data[PrAcc] = 1;
ejctrl->in->data[ProbEn] = 1;
ejctrl->in->data[DmaAcc] = 1;
urj_tap_chain_shift_data_registers (bus->chain, 1);
urj_log (URJ_LOG_LEVEL_ALL, "Wrote to ejctrl->in =%s %08lX\n",
urj_tap_register_get_string (ejctrl->in),
(long unsigned) reg_value (ejctrl->in));
urj_log (URJ_LOG_LEVEL_ALL, "Read from ejctrl->out =%s %08lX\n",
urj_tap_register_get_string (ejctrl->out),
(long unsigned) reg_value (ejctrl->out));
timeout--;
if (!timeout)
break;
}
while (ejctrl->out->data[DstRt] == 1); // This flag tell us the processor has completed the op
urj_part_set_instruction (bus->part, "EJTAG_DATA");
urj_tap_chain_shift_instructions (bus->chain);
urj_tap_register_fill (ejdata->in, 0);
urj_tap_chain_shift_data_registers (bus->chain, 1);
ret = reg_value (ejdata->out);
urj_log (URJ_LOG_LEVEL_COMM, "Read from ejdata->out(%c) =%s %08lX\n",
siz_ (sz), urj_tap_register_get_string (ejdata->out),
(long unsigned) reg_value (ejdata->out));
urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
urj_tap_chain_shift_instructions (bus->chain);
urj_tap_register_fill (ejctrl->in, 0);
ejctrl->in->data[PrAcc] = 1;
ejctrl->in->data[ProbEn] = 1;
urj_tap_chain_shift_data_registers (bus->chain, 1); // Disable DMA, reset state to previous one.
urj_log (URJ_LOG_LEVEL_ALL, "Wrote to ejctrl->in =%s %08lX\n",
urj_tap_register_get_string (ejctrl->in),
(long unsigned) reg_value (ejctrl->in));
urj_log (URJ_LOG_LEVEL_ALL, "Read from ejctrl->out =%s %08lX\n",
urj_tap_register_get_string (ejctrl->out),
(long unsigned) reg_value(ejctrl->out));
if (ejctrl->out->data[Derr] == 1)
{ // Check for DMA error, i.e. incorrect address
urj_error_set (URJ_ERROR_BUS_DMA,
_("dma read (dma transaction failed)"));
}
switch (sz)
{
case DMA_HALFWORD:
if (addr & 2)
ret = (ret >> 16) & 0xffff;
else
ret = ret & 0xffff;
break;
case DMA_BYTE:
if ((addr & 3) == 3)
ret = (ret >> 24) & 0xff;
else if ((addr & 3) == 2)
/**
* low-level dma write
*
*/
static void
ejtag_dma_write (urj_bus_t *bus, unsigned int addr, unsigned int data, int sz)
{
static urj_data_register_t *ejctrl = NULL;
static urj_data_register_t *ejaddr = NULL;
static urj_data_register_t *ejdata = NULL;
int i = 0;
int timeout = 5;
if (ejctrl == NULL)
ejctrl = urj_part_find_data_register (bus->part, "EJCONTROL");
if (ejaddr == NULL)
ejaddr = urj_part_find_data_register (bus->part, "EJADDRESS");
if (ejdata == NULL)
ejdata = urj_part_find_data_register (bus->part, "EJDATA");
switch (sz)
{ /* Fill the other bytes with copy of the current */
case DMA_BYTE:
data &= 0xff;
data |= (data << 8) | (data << 16) | (data << 24);
break;
case DMA_HALFWORD:
data &= 0xffff;
data |= (data << 16);
break;
default:
break;
}
urj_part_set_instruction (bus->part, "EJTAG_ADDRESS");
urj_tap_chain_shift_instructions (bus->chain);
for (i = 0; i < 32; i++)
ejaddr->in->data[i] = (addr >> i) & 1;
urj_tap_chain_shift_data_registers (bus->chain, 0); /* Push the address to write */
urj_log (URJ_LOG_LEVEL_COMM, "Wrote to ejaddr->in =%s %08lX\n",
urj_tap_register_get_string (ejaddr->in),
(long unsigned) reg_value (ejaddr->in));
urj_part_set_instruction (bus->part, "EJTAG_DATA");
urj_tap_chain_shift_instructions (bus->chain);
for (i = 0; i < 32; i++)
ejdata->in->data[i] = (data >> i) & 1;
urj_tap_chain_shift_data_registers (bus->chain, 0); /* Push the data to write */
urj_log (URJ_LOG_LEVEL_COMM, "Wrote to edata->in(%c) =%s %08lX\n",
siz_ (sz), urj_tap_register_get_string (ejdata->in),
(long unsigned) reg_value (ejdata->in));
urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
urj_tap_chain_shift_instructions (bus->chain);
urj_tap_register_fill (ejctrl->in, 0);
ejctrl->in->data[PrAcc] = 1; // Processor access
ejctrl->in->data[ProbEn] = 1;
ejctrl->in->data[DmaAcc] = 1; // DMA operation request */
ejctrl->in->data[DstRt] = 1;
if (sz)
ejctrl->in->data[sz] = 1; // Size : can be WORD/HALFWORD or nothing for byte
urj_tap_chain_shift_data_registers (bus->chain, 0); /* Do the operation */
urj_log (URJ_LOG_LEVEL_ALL, "Wrote to ejctrl->in =%s %08lX\n",
urj_tap_register_get_string (ejctrl->in),
(long unsigned) reg_value (ejctrl->in));
do
{
urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
urj_tap_chain_shift_instructions (bus->chain);
urj_tap_register_fill (ejctrl->in, 0);
ejctrl->in->data[PrAcc] = 1;
ejctrl->in->data[ProbEn] = 1;
ejctrl->in->data[DmaAcc] = 1;
urj_tap_chain_shift_data_registers (bus->chain, 1);
timeout--;
if (!timeout)
break;
}
while (ejctrl->out->data[DstRt] == 1); // This flag tell us the processor has completed the op
urj_part_set_instruction (bus->part, "EJTAG_CONTROL");
urj_tap_chain_shift_instructions (bus->chain);
urj_tap_register_fill (ejctrl->in, 0);
ejctrl->in->data[PrAcc] = 1;
ejctrl->in->data[ProbEn] = 1;
urj_tap_chain_shift_data_registers (bus->chain, 1); // Disable DMA, reset state to previous one.
if (ejctrl->out->data[Derr] == 1)
{ // Check for DMA error, i.e. incorrect address
urj_error_set (URJ_ERROR_BUS_DMA,
_("dma write (dma transaction failed)"));
}
return;
}
