static void __init omap_4430sdp_init(void)
{
int status;
int package = OMAP_PACKAGE_CBS;
if (omap_rev() == OMAP4430_REV_ES1_0)
package = OMAP_PACKAGE_CBL;
omap4_mux_init(board_mux, package);
omap4_i2c_init();
omap_sfh7741prox_init();
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
omap_serial_init();
omap4_twl6030_hsmmc_init(mmc);
/* OMAP4 SDP uses internal transceiver so register nop transceiver */
usb_nop_xceiv_register(0);
/* FIXME: allow multi-omap to boot until musb is updated for omap4 */
if (!cpu_is_omap44xx())
usb_musb_init(&musb_board_data);
status = omap_ethernet_init();
if (status) {
pr_err("Ethernet initialization failed: %d\n", status);
} else {
sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
spi_register_board_info(sdp4430_spi_board_info,
ARRAY_SIZE(sdp4430_spi_board_info));
}
}
static void __init omap3_evm_init(void)
{
struct omap_board_mux *obm;
omap3_evm_get_revision();
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
omap3_mux_init(obm, OMAP_PACKAGE_CBB);
omap_mux_init_gpio(63, OMAP_PIN_INPUT);
omap_hsmmc_init(mmc);
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
omap3evm_twldata.vaux2 = &omap3evm_vaux2;
omap3_evm_i2c_init();
omap_display_init(&omap3_evm_dss_data);
omap_serial_init();
omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
/* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
usb_nop_xceiv_register();
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
/* enable EHCI VBUS using GPIO22 */
omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP);
/* Select EHCI port on main board */
omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT,
OMAP_PIN_INPUT_PULLUP);
gpio_request_array(omap3_evm_ehci_gpios,
ARRAY_SIZE(omap3_evm_ehci_gpios));
/* setup EHCI phy reset config */
omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
usbhs_bdata.reset_gpio_port[1] = 21;
/* EVM REV >= E can supply 500mA with EXTVBUS programming */
musb_board_data.power = 500;
musb_board_data.extvbus = 1;
} else {
/* setup EHCI phy reset on MDC */
omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
usbhs_bdata.reset_gpio_port[1] = 135;
}
usb_musb_init(&musb_board_data);
usbhs_init(&usbhs_bdata);
omap_nand_flash_init(NAND_BUSWIDTH_16, omap3evm_nand_partitions,
ARRAY_SIZE(omap3evm_nand_partitions));
omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
omap3evm_init_smsc911x();
omap3_evm_display_init();
omap3_evm_wl12xx_init();
omap_twl4030_audio_init("omap3evm");
}
static void __init omap3_evm_init(void)
{
omap3_evm_get_revision();
if (cpu_is_omap3630())
omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
else
omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
omap_board_config = omap3_evm_config;
omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
omap3_evm_i2c_init();
omap_display_init(&omap3_evm_dss_data);
omap_serial_init();
omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
/* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
usb_nop_xceiv_register();
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
/* enable EHCI VBUS using GPIO22 */
omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP);
/* Select EHCI port on main board */
omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT,
OMAP_PIN_INPUT_PULLUP);
gpio_request_array(omap3_evm_ehci_gpios,
ARRAY_SIZE(omap3_evm_ehci_gpios));
/* setup EHCI phy reset config */
omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
usbhs_bdata.reset_gpio_port[1] = 21;
/* EVM REV >= E can supply 500mA with EXTVBUS programming */
musb_board_data.power = 500;
musb_board_data.extvbus = 1;
} else {
/* setup EHCI phy reset on MDC */
omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
usbhs_bdata.reset_gpio_port[1] = 135;
}
usb_musb_init(&musb_board_data);
usbhs_init(&usbhs_bdata);
omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
omap3evm_init_smsc911x();
omap3_evm_display_init();
#ifdef CONFIG_WL12XX_PLATFORM_DATA
/* WL12xx WLAN Init */
if (wl12xx_set_platform_data(&omap3evm_wlan_data))
pr_err("error setting wl12xx data\n");
platform_device_register(&omap3evm_wlan_regulator);
#endif
}
static void __init omap3_evm_init(void)
{
omap3_evm_get_revision();
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
omap3evm_twldata.vaux2 = &omap3evm_vaux2;
else
omap3evm_twldata.vusb = &omap3_evm_vusb;
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3_evm_i2c_init();
platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
spi_register_board_info(omap3evm_spi_board_info,
ARRAY_SIZE(omap3evm_spi_board_info));
omap_serial_init();
/* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
usb_nop_xceiv_register();
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
/* enable EHCI VBUS using GPIO22 */
omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP);
gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS");
gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0);
gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1);
/* Select EHCI port on main board */
omap_mux_init_gpio(61, OMAP_PIN_INPUT_PULLUP);
gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port");
gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0);
gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0);
/* setup EHCI phy reset config */
omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
ehci_pdata.reset_gpio_port[1] = 21;
/* EVM REV >= E can supply 500mA with EXTVBUS programming */
musb_board_data.power = 500;
musb_board_data.extvbus = 1;
} else {
/* setup EHCI phy reset on MDC */
omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
ehci_pdata.reset_gpio_port[1] = 135;
}
usb_musb_init(&musb_board_data);
usb_ehci_init(&ehci_pdata);
ads7846_dev_init();
omap3evm_init_smsc911x();
omap3_evm_display_init();
}
static int dsps_musb_init(struct musb *musb)
{
struct device *dev = musb->controller;
struct musb_hdrc_platform_data *plat = dev->platform_data;
struct platform_device *pdev = to_platform_device(dev);
struct dsps_glue *glue = dev_get_drvdata(dev->parent);
const struct dsps_musb_wrapper *wrp = glue->wrp;
struct omap_musb_board_data *data = plat->board_data;
void __iomem *reg_base = musb->ctrl_base;
u32 rev, val;
int status;
/* mentor core register starts at offset of 0x400 from musb base */
musb->mregs += wrp->musb_core_offset;
/* NOP driver needs change if supporting dual instance */
usb_nop_xceiv_register();
musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
if (IS_ERR_OR_NULL(musb->xceiv))
return -ENODEV;
/* Returns zero if e.g. not clocked */
rev = dsps_readl(reg_base, wrp->revision);
if (!rev) {
status = -ENODEV;
goto err0;
}
setup_timer(&glue->timer[pdev->id], otg_timer, (unsigned long) musb);
/* Reset the musb */
dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
data->set_phy_power(1);
musb->isr = dsps_interrupt;
/* reset the otgdisable bit, needed for host mode to work */
val = dsps_readl(reg_base, wrp->phy_utmi);
val &= ~(1 << wrp->otg_disable);
dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
/* clear level interrupt */
dsps_writel(reg_base, wrp->eoi, 0);
return 0;
err0:
usb_put_phy(musb->xceiv);
usb_nop_xceiv_unregister();
return status;
}
static void __init omap3_evm_init(void)
{
omap3_evm_get_revision();
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3_evm_i2c_init();
platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
spi_register_board_info(omap3evm_spi_board_info,
ARRAY_SIZE(omap3evm_spi_board_info));
omap_serial_init();
#ifdef CONFIG_NOP_USB_XCEIV
/* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
usb_nop_xceiv_register();
#endif
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
/* enable EHCI VBUS using GPIO22 */
omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP);
gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS");
gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0);
gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1);
/* Select EHCI port on main board */
omap_mux_init_gpio(61, OMAP_PIN_INPUT_PULLUP);
gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port");
gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0);
gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0);
/* setup EHCI phy reset config */
omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
ehci_pdata.reset_gpio_port[1] = 21;
} else {
/* setup EHCI phy reset on MDC */
omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
ehci_pdata.reset_gpio_port[1] = 135;
/* MDC also need VUSB1V5 regulator */
ehci_pdata.aux[1] = 1;
}
usb_musb_init();
usb_ehci_init(&ehci_pdata);
ads7846_dev_init();
omap3evm_init_smsc911x();
}
static void __init omap3_evm_init(void)
{
omap3_evm_i2c_init();
platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
spi_register_board_info(omap3evm_spi_board_info,
ARRAY_SIZE(omap3evm_spi_board_info));
omap_serial_init();
#ifdef CONFIG_NOP_USB_XCEIV
/* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
usb_nop_xceiv_register();
#endif
usb_musb_init();
ads7846_dev_init();
}
static int am35x_musb_init(struct musb *musb)
{
struct device *dev = musb->controller;
struct musb_hdrc_platform_data *plat = dev->platform_data;
struct omap_musb_board_data *data = plat->board_data;
void __iomem *reg_base = musb->ctrl_base;
u32 rev;
musb->mregs += USB_MENTOR_CORE_OFFSET;
/* Returns zero if e.g. not clocked */
rev = musb_readl(reg_base, USB_REVISION_REG);
if (!rev)
return -ENODEV;
usb_nop_xceiv_register();
musb->xceiv = otg_get_transceiver();
if (!musb->xceiv)
return -ENODEV;
if (is_host_enabled(musb))
setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
/* Reset the musb */
if (data->reset)
data->reset();
/* Reset the controller */
musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
data->set_phy_power(1);
msleep(5);
musb->isr = am35x_musb_interrupt;
/* clear level interrupt */
if (data->clear_irq)
data->clear_irq();
return 0;
}
static int da8xx_musb_init(struct musb *musb)
{
void __iomem *reg_base = musb->ctrl_base;
u32 rev;
int ret = -ENODEV;
musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
/* Returns zero if e.g. not clocked */
rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
if (!rev)
goto fail;
usb_nop_xceiv_register();
musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
if (IS_ERR_OR_NULL(musb->xceiv)) {
ret = -EPROBE_DEFER;
goto fail;
}
setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
/* Reset the controller */
musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
/* Start the on-chip PHY and its PLL. */
phy_on();
msleep(5);
/* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
rev, __raw_readl(CFGCHIP2),
musb_readb(reg_base, DA8XX_USB_CTRL_REG));
musb->isr = da8xx_musb_interrupt;
return 0;
fail:
return ret;
}
static void __init omap_4430sdp_init(void)
{
int status;
omap4_i2c_init();
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
omap_serial_init();
omap4_twl6030_hsmmc_init(mmc);
/* OMAP4 SDP uses internal transceiver so register nop transceiver */
usb_nop_xceiv_register();
if (!cpu_is_omap44xx())
usb_musb_init(&musb_board_data);
status = omap_ethernet_init();
if (status) {
pr_err("Ethernet initialization failed: %d\n", status);
} else {
sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
spi_register_board_info(sdp4430_spi_board_info,
ARRAY_SIZE(sdp4430_spi_board_info));
}
}
int __init musb_platform_init(struct musb *musb)
{
usb_nop_xceiv_register();
/* We require some kind of external transceiver, hooked
* up through ULPI. TWL4030-family PMICs include one,
* which needs a driver, drivers aren't always needed.
*/
musb->xceiv = otg_get_transceiver();
if (!musb->xceiv) {
pr_err("HS USB OTG: no transceiver configured\n");
return -ENODEV;
}
m2s_usb_platform_resume(musb);
m2s_usb_vbus_power(musb, musb->board_mode == MUSB_HOST, 1);
if (is_host_enabled(musb))
musb->board_set_vbus = m2s_usb_vbus_set;
return 0;
}
static int davinci_musb_init(struct musb *musb)
{
void __iomem *tibase = musb->ctrl_base;
u32 revision;
int ret = -ENODEV;
usb_nop_xceiv_register();
musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
if (IS_ERR_OR_NULL(musb->xceiv)) {
ret = -EPROBE_DEFER;
goto unregister;
}
musb->mregs += DAVINCI_BASE_OFFSET;
/* returns zero if e.g. not clocked */
revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
if (revision == 0)
goto fail;
setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
davinci_musb_source_power(musb, 0, 1);
/* dm355 EVM swaps D+/D- for signal integrity, and
* is clocked from the main 24 MHz crystal.
*/
if (machine_is_davinci_dm355_evm()) {
u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
phy_ctrl &= ~(3 << 9);
phy_ctrl |= USBPHY_DATAPOL;
__raw_writel(phy_ctrl, USB_PHY_CTRL);
}
/* On dm355, the default-A state machine needs DRVVBUS control.
* If we won't be a host, there's no need to turn it on.
*/
if (cpu_is_davinci_dm355()) {
u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
deepsleep &= ~DRVVBUS_FORCE;
__raw_writel(deepsleep, DM355_DEEPSLEEP);
}
/* reset the controller */
musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
/* start the on-chip PHY and its PLL */
phy_on();
msleep(5);
/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
revision, __raw_readl(USB_PHY_CTRL),
musb_readb(tibase, DAVINCI_USB_CTRL_REG));
musb->isr = davinci_musb_interrupt;
return 0;
fail:
usb_put_phy(musb->xceiv);
unregister:
usb_nop_xceiv_unregister();
return ret;
}
int __init musb_platform_init(struct musb *musb)
{
void __iomem *tibase = musb->ctrl_base;
u32 revision;
usb_nop_xceiv_register();
musb->xceiv = otg_get_transceiver();
if (!musb->xceiv)
return -ENODEV;
musb->mregs += DAVINCI_BASE_OFFSET;
clk_enable(musb->clock);
/* returns zero if e.g. not clocked */
revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
if (revision == 0)
goto fail;
if (is_host_enabled(musb))
setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
musb->board_set_vbus = davinci_set_vbus;
davinci_source_power(musb, 0, 1);
/* dm355 EVM swaps D+/D- for signal integrity, and
* is clocked from the main 24 MHz crystal.
*/
if (machine_is_davinci_dm355_evm()) {
u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
phy_ctrl &= ~(3 << 9);
phy_ctrl |= USBPHY_DATAPOL;
__raw_writel(phy_ctrl, USB_PHY_CTRL);
}
/* On dm355, the default-A state machine needs DRVVBUS control.
* If we won't be a host, there's no need to turn it on.
*/
if (cpu_is_davinci_dm355()) {
u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
if (is_host_enabled(musb)) {
deepsleep &= ~DRVVBUS_OVERRIDE;
} else {
deepsleep &= ~DRVVBUS_FORCE;
deepsleep |= DRVVBUS_OVERRIDE;
}
__raw_writel(deepsleep, DM355_DEEPSLEEP);
}
/* reset the controller */
musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
/* start the on-chip PHY and its PLL */
phy_on();
msleep(5);
/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
revision, __raw_readl(USB_PHY_CTRL),
musb_readb(tibase, DAVINCI_USB_CTRL_REG));
musb->isr = davinci_interrupt;
return 0;
fail:
usb_nop_xceiv_unregister();
return -ENODEV;
}
static int dsps_musb_init(struct musb *musb)
{
struct device *dev = musb->controller;
struct platform_device *pdev = to_platform_device(dev);
struct dsps_glue *glue = dev_get_drvdata(dev->parent);
const struct dsps_musb_wrapper *wrp = glue->wrp;
void __iomem *reg_base = musb->ctrl_base;
u32 rev, val;
int status;
/* mentor core register starts at offset of 0x400 from musb base */
musb->mregs += wrp->musb_core_offset;
#if 1
/* NOP driver needs change if supporting dual instance */
if(!pdev->id) {
usb_nop_xceiv_register();
}
musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
#else
/* Get the NOP PHY */
sprintf(name, "usb%d-phy", pdev->id);
musb->xceiv = devm_usb_get_phy_by_phandle(&parent_pdev->dev, name);
#endif
if (IS_ERR_OR_NULL(musb->xceiv)) {
dev_err(dev, "%s:%d %s: FAIL\n", __FILE__, __LINE__, __func__);
return -EPROBE_DEFER;
}
/* Returns zero if e.g. not clocked */
rev = dsps_readl(reg_base, wrp->revision);
if (!rev) {
dev_err(dev, "%s:%d %s: FAIL\n", __FILE__, __LINE__, __func__);
status = -ENODEV;
goto err0;
}
dev_info(dev, "pdev->id = %d\n", pdev->id);
setup_timer(&glue->timer[pdev->id], otg_timer, (unsigned long) musb);
/* Reset the musb */
dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
/* Start the on-chip PHY and its PLL. */
musb_dsps_phy_control(glue, pdev->id, 1);
musb->isr = dsps_interrupt;
/* reset the otgdisable bit, needed for host mode to work */
val = dsps_readl(reg_base, wrp->phy_utmi);
val &= ~(1 << wrp->otg_disable);
dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
/* clear level interrupt */
dsps_writel(reg_base, wrp->eoi, 0);
dev_info(dev, "%s:%d %s: OK\n", __FILE__, __LINE__, __func__);
return 0;
err0:
usb_put_phy(musb->xceiv);
if(!pdev->id) {
usb_nop_xceiv_unregister();
}
return status;
}
static void __init VAR_SOM_OM3X_init(void)
{
VAR_SOM_OM3X_twldata.vaux2 = &VAR_SOM_OM3X_vaux2;
omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
// USB phy enable
if (gpio_request(24,"GPIO24")<0)
printk(KERN_ERR "Can't get GPIO24 for USB phy reset\n");
gpio_direction_output(24, 1);
gpio_set_value(24, 1);
// SMSC 9221 interrupt
if (gpio_request(29,"GPIO29")<0)
printk(KERN_ERR "Can't get GPIO29 for ETH0\n");
gpio_direction_input(29);
#if 0
#ifdef VER_2_1
omap_mux_init_gpio(VAR_SOM_OM3X_USB3_PWR_ENn, OMAP_PIN_INPUT_PULLUP);
if (gpio_request(VAR_SOM_OM3X_USB3_PWR_ENn,"USB3_PWR_ENn")<0)
printk(KERN_ERR "Can't get 167 for USB3 power enable\n");
gpio_direction_output(VAR_SOM_OM3X_USB3_PWR_ENn, 1);
gpio_set_value(VAR_SOM_OM3X_USB3_PWR_ENn, 1);
#endif
#endif
VAR_SOM_OM3X_i2c_init();
platform_add_devices(VAR_SOM_OM3X_devices, ARRAY_SIZE(VAR_SOM_OM3X_devices));
#if defined (CONFIG_TOUCHSCREEN_CTW6120) || defined (CONFIG_TOUCHSCREEN_ADS7846)
spi_register_board_info(VAR_SOM_OM3X_spi_board_info,
ARRAY_SIZE(VAR_SOM_OM3X_spi_board_info));
#endif
omap_serial_init();
#ifdef CONFIG_NOP_USB_XCEIV
usb_nop_xceiv_register();
#endif
omap_mux_init_gpio(VAR_SOM_OM3X_DVI_PANEL_EN_GPIO, OMAP_PIN_INPUT_PULLUP);
usb_musb_init();
usb_ehci_init(&ehci_pdata);
VAR_SOM_OM3X_flash_init();
ads7846_dev_init();
ctw6120_dev_init();
VAR_SOM_OM3X_init_smsc911x();
#ifdef CONFIG_PANEL_VARISCITE
VAR_SOM_OM3X_display_init();
#endif
/* Ensure SDRC pins are mux'd for self-refresh */
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
/* Push Buttons */
bp_add_device_buttons();
}
static int __devinit dwc_otg_driver_probe(struct platform_device *ofdev)
{
int retval;
struct dwc_otg_device *dwc_dev;
struct device *dev = &ofdev->dev;
struct resource res;
ulong gusbcfg_addr;
u32 usbcfg = 0;
struct resource *nres = 0;
#ifdef CONFIG_OF
u32 prop;
u32 prop_array[15];
#endif
dwc_dev = kzalloc(sizeof(*dwc_dev), GFP_KERNEL);
if (!dwc_dev) {
dev_err(dev, "kmalloc of dwc_otg_device failed\n");
retval = -ENOMEM;
goto fail_dwc_dev;
}
/* Retrieve the memory and IRQ resources. */
dwc_dev->irq = platform_get_irq(ofdev, 0);
if (dwc_dev->irq == NO_IRQ) {
dev_err(dev, "no device irq\n");
retval = -ENODEV;
goto fail_of_irq;
}
nres = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
res = *nres;
if(nres == 0) {
dev_err(dev, "%s: Can't get USB-OTG register address\n",
__func__);
retval = -ENOMEM;
goto fail_of_irq;
}
dwc_dev->phys_addr = res.start;
dwc_dev->base_len = res.end - res.start + 1;
if (!request_mem_region(dwc_dev->phys_addr,
dwc_dev->base_len, dwc_driver_name)) {
dev_err(dev, "request_mem_region failed\n");
retval = -EBUSY;
goto fail_of_irq;
}
/* Map the DWC_otg Core memory into virtual address space. */
dwc_dev->base = ioremap(platform_get_resource(ofdev, IORESOURCE_MEM, 0)->start, SZ_256K);
if (!dwc_dev->base) {
dev_err(dev, "ioremap() failed\n");
retval = -ENOMEM;
goto fail_ioremap;
}
dev_dbg(dev, "mapped base=0x%08x\n", (__force u32)dwc_dev->base);
/*
* Initialize driver data to point to the global DWC_otg
* Device structure.
*/
dev_set_drvdata(dev, dwc_dev);//driver
dwc_dev->core_if =
dwc_otg_cil_init(dwc_dev->base, &dwc_otg_module_params);
if (!dwc_dev->core_if) {
dev_err(dev, "CIL initialization failed!\n");
retval = -ENOMEM;
goto fail_cil_init;
}
/*
* Set the wqfunc of this core_if as "not set"
*/
dwc_dev->core_if->wqfunc_setup_done = 0;
/*
* Validate parameter values after dwc_otg_cil_init.
*/
if (check_parameters(dwc_dev->core_if)) {
retval = -EINVAL;
goto fail_check_param;
}
#ifdef CONFIG_OF
if(!of_property_read_u32(ofdev->dev.of_node,
"dma-mask", (u32*)&dwc_otg_dma_mask)) {
dev->dma_mask = &dwc_otg_dma_mask;
}
else {
dev->dma_mask = NULL;
}
if(!of_property_read_u32(ofdev->dev.of_node,
"ulpi-ddr", &prop)) {
dwc_otg_module_params.phy_ulpi_ddr = prop;
}
if(!of_property_read_u32(ofdev->dev.of_node,
"host-rx-fifo-size", &prop)) {
dwc_otg_module_params.host_rx_fifo_size = prop;
}
if(!of_property_read_u32(ofdev->dev.of_node,
"dev-rx-fifo-size", &prop)) {
dwc_otg_module_params.dev_rx_fifo_size = prop;
}
if(!of_property_read_u32(ofdev->dev.of_node,
"host-nperio-tx-fifo-size", &prop)) {
dwc_otg_module_params.host_nperio_tx_fifo_size = prop;
}
if(!of_property_read_u32(ofdev->dev.of_node,
"dev-nperio-tx-fifo-size", &prop)) {
dwc_otg_module_params.dev_nperio_tx_fifo_size = prop;
}
if(!of_property_read_u32(ofdev->dev.of_node,
"host-perio-tx-fifo-size", &prop)) {
dwc_otg_module_params.host_perio_tx_fifo_size = prop;
}
if(!of_property_read_u32_array(ofdev->dev.of_node,
"dev-perio-tx-fifo-size", prop_array, MAX_PERIO_FIFOS)) {
int i;
for(i=0; i<MAX_PERIO_FIFOS; i++)
dwc_otg_module_params.dev_tx_fifo_size[i]
= prop_array[i];
}
if(!of_property_read_u32_array(ofdev->dev.of_node,
"dev-tx-fifo-size", prop_array, MAX_TX_FIFOS)) {
int i;
for(i=0; i<MAX_TX_FIFOS; i++)
dwc_otg_module_params.dev_perio_tx_fifo_size[i]
= prop_array[i];
}
#endif
usb_nop_xceiv_register();
dwc_dev->core_if->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
if (!dwc_dev->core_if->xceiv) {
retval = -ENODEV;
goto fail_xceiv;
}
dwc_set_feature(dwc_dev->core_if);
/* Initialize the DWC_otg core. */
dwc_otg_core_init(dwc_dev->core_if);
/*
* Disable the global interrupt until all the interrupt
* handlers are installed.
*/
spin_lock(&dwc_dev->lock);
dwc_otg_disable_global_interrupts(dwc_dev->core_if);
spin_unlock(&dwc_dev->lock);
/*
* Install the interrupt handler for the common interrupts before
* enabling common interrupts in core_init below.
*/
retval = request_irq(dwc_dev->irq, dwc_otg_common_irq,
IRQF_SHARED, "dwc_otg", dwc_dev);
if (retval) {
dev_err(dev, "request of irq%d failed retval: %d\n",
dwc_dev->irq, retval);
retval = -EBUSY;
goto fail_req_irq;
} else {
dwc_dev->common_irq_installed = 1;
}
if (!dwc_has_feature(dwc_dev->core_if, DWC_HOST_ONLY)) {
//if (dwc_has_feature(dwc_dev->core_if, DWC_DEVICE_ONLY)) {
/* Initialize the PCD */
retval = dwc_otg_pcd_init(dev);
if (retval) {
dev_err(dev, "dwc_otg_pcd_init failed\n");
dwc_dev->pcd = NULL;
goto fail_req_irq;
}
}
gusbcfg_addr = (ulong) (dwc_dev->core_if->core_global_regs)
+ DWC_GUSBCFG;
if (!dwc_has_feature(dwc_dev->core_if, DWC_DEVICE_ONLY)) {
//if (dwc_has_feature(dwc_dev->core_if, DWC_HOST_ONLY)) {
/* Initialize the HCD and force_host_mode */
usbcfg = dwc_reg_read(gusbcfg_addr, 0);
usbcfg |= DWC_USBCFG_FRC_HST_MODE;
dwc_reg_write(gusbcfg_addr, 0, usbcfg);
retval = dwc_otg_hcd_init(dev, dwc_dev);
if (retval) {
dev_err(dev, "dwc_otg_hcd_init failed\n");
dwc_dev->hcd = NULL;
goto fail_hcd;
}
/* configure chargepump interrupt */
dwc_dev->hcd->cp_irq = platform_get_irq_byname(ofdev, "chargepumpirq");
if(dwc_dev->hcd->cp_irq != -ENXIO) {
retval = request_irq(dwc_dev->hcd->cp_irq,
dwc_otg_externalchgpump_irq,
IRQF_SHARED,
"dwc_otg_ext_chg_pump", dwc_dev);
if (retval) {
dev_err(dev,
"request of irq failed retval: %d\n",
retval);
retval = -EBUSY;
goto fail_hcd;
} else {
dev_dbg(dev, "%s: ExtChgPump Detection "
"IRQ registered\n", dwc_driver_name);
}
}
}
/*
* Enable the global interrupt after all the interrupt
* handlers are installed.
*/
dwc_otg_enable_global_interrupts(dwc_dev->core_if);
#if 0
usbcfg = dwc_reg_read(gusbcfg_addr, 0);
usbcfg &= ~DWC_USBCFG_FRC_HST_MODE;
dwc_reg_write(gusbcfg_addr, 0, usbcfg);
#endif
return 0;
fail_hcd:
free_irq(dwc_dev->irq, dwc_dev);
if (!dwc_has_feature(dwc_dev->core_if, DWC_HOST_ONLY)) {
if (dwc_dev->pcd)
dwc_otg_pcd_remove(dev);
}
fail_req_irq:
usb_put_phy(dwc_dev->core_if->xceiv);
fail_xceiv:
usb_nop_xceiv_unregister();
fail_check_param:
dwc_otg_cil_remove(dwc_dev->core_if);
fail_cil_init:
dev_set_drvdata(dev, NULL);
iounmap(dwc_dev->base);
fail_ioremap:
release_mem_region(dwc_dev->phys_addr, dwc_dev->base_len);
fail_of_irq:
kfree(dwc_dev);
fail_dwc_dev:
return retval;
}
static int davinci_musb_init(struct musb *musb)
{
void __iomem *tibase = musb->ctrl_base;
u32 revision;
usb_nop_xceiv_register();
musb->xceiv = usb_get_transceiver();
if (!musb->xceiv)
goto unregister;
musb->mregs += DAVINCI_BASE_OFFSET;
revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
if (revision == 0)
goto fail;
if (is_host_enabled(musb))
setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
davinci_musb_source_power(musb, 0, 1);
if (machine_is_davinci_dm355_evm()) {
u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
phy_ctrl &= ~(3 << 9);
phy_ctrl |= USBPHY_DATAPOL;
__raw_writel(phy_ctrl, USB_PHY_CTRL);
}
if (cpu_is_davinci_dm355()) {
u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
if (is_host_enabled(musb)) {
deepsleep &= ~DRVVBUS_OVERRIDE;
} else {
deepsleep &= ~DRVVBUS_FORCE;
deepsleep |= DRVVBUS_OVERRIDE;
}
__raw_writel(deepsleep, DM355_DEEPSLEEP);
}
musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
phy_on();
msleep(5);
pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
revision, __raw_readl(USB_PHY_CTRL),
musb_readb(tibase, DAVINCI_USB_CTRL_REG));
musb->isr = davinci_musb_interrupt;
return 0;
fail:
usb_put_transceiver(musb->xceiv);
unregister:
usb_nop_xceiv_unregister();
return -ENODEV;
}
/**
* musb_platform_init() - Initialize the platform USB driver.
* @musb: struct musb pointer.
*
* This function initialize the USB controller and Phy.
*/
int __init musb_platform_init(struct musb *musb, void *board_data)
{
int ret;
usb_nop_xceiv_register();
musb->xceiv = otg_get_transceiver();
if (!musb->xceiv) {
pr_err("U8500 USB : no transceiver configured\n");
ret = -ENODEV;
goto cleanup0;
}
ret = musb_stm_hs_otg_init(musb);
if (ret < 0) {
pr_err("U8500 USB: Failed to init the OTG object\n");
goto cleanup1;
}
if (is_host_enabled(musb))
musb->board_set_vbus = set_vbus;
if (is_peripheral_enabled(musb))
musb->xceiv->set_power = set_power;
ret = musb_phy_en(musb->board_mode);
if (ret < 0) {
pr_err("U8500 USB: Failed to enable PHY\n");
goto cleanup1;
}
if (musb_status == NULL) {
musb_status = musb;
spin_lock_init(&musb_ulpi_spinlock);
}
/* Registering usb device for sysfs */
usbstatus_kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
if (usbstatus_kobj == NULL) {
ret = -ENOMEM;
goto cleanup1;
}
usbstatus_kobj->ktype = &ktype_usbstatus;
kobject_init(usbstatus_kobj, usbstatus_kobj->ktype);
ret = kobject_set_name(usbstatus_kobj, "usb_status");
if (ret)
goto cleanup2;
ret = kobject_add(usbstatus_kobj, NULL, "usb_status");
if (ret) {
goto cleanup2;
}
if (musb->board_mode != MUSB_PERIPHERAL) {
init_timer(¬ify_timer);
notify_timer.expires = jiffies + msecs_to_jiffies(1000);
notify_timer.function = funct_host_notify_timer;
notify_timer.data = (unsigned long)musb;
add_timer(¬ify_timer);
}
stm_usb_power_wq = create_singlethread_workqueue(
"stm_usb_power_wq");
if (stm_usb_power_wq == NULL) {
ret = -ENOMEM;
goto cleanup2;
}
INIT_WORK(&stm_prcmu_qos, stm_prcmu_qos_work);
ret = musb_force_detect(musb->board_mode);
if (ret < 0)
goto cleanup2;
return 0;
cleanup2:
kfree(usbstatus_kobj);
if (musb->board_mode != MUSB_PERIPHERAL)
del_timer_sync(¬ify_timer);
cleanup1:
otg_put_transceiver(musb->xceiv);
cleanup0:
usb_nop_xceiv_unregister();
return ret;
}
