static void timer_enable(uint8_t u8Timer) {
uint32_t u32TimerMask = 0;
uint8_t u8IntEnableMask = 0U;
if(u8Timer == E_AHI_TIMER_1) {
u32TimerMask = REG_SYSCTRL_PWRCTRL_T1EN_MASK;
}
else if(u8Timer == E_AHI_TIMER_2) {
u32TimerMask = REG_SYSCTRL_PWRCTRL_T2EN_MASK;
}
/* Activate timer block by writing to the REG_SYS_PWR_CTRL register the
timer to be enabled. read/modify/ write */
vREG_SysWrite(REG_SYS_PWR_CTRL,u32REG_SysRead(REG_SYS_PWR_CTRL) | u32TimerMask);
/*Do extra wishbone read to make sure timer is enabled*/
(volatile uint32_t)u32REG_SysRead(REG_SYS_PWR_CTRL);
/* Set control to default (internal clock) */
vREG_TimerWrite(u8Timer, REG_TMR_CTRL, 0);
/* Clear any pending interrupts by writing to the interrupt register */
vREG_TimerWrite(u8Timer, REG_TMR_INT, REG_TMR_INT_L_EN_MASK | REG_TMR_INT_P_EN_MASK);
/* Enable interrupt to trigger on falling edge of end of period */
U8_SET_BITS(&u8IntEnableMask, REG_TMR_INT_P_EN_MASK);
/* Set interrupt enable register */
vREG_TimerWrite(u8Timer, REG_TMR_INTE, (uint32_t)u8IntEnableMask);
}
/****************************************************************************
*
* NAME: vHandleOperationalState
*
* DESCRIPTION:
* Send the appropriate commands in operational mode
*
* RETURNS:
* void
*
****************************************************************************/
void vHandleOperationalState(uint8 u8CmdId)
{
#ifndef DK4
sGPDData.u8ButtonCount = u32REG_SysRead(REG_SYS_WK_T1);
#endif
#ifdef GPD_SEND_DECOMM_CMD
if((DECOMMISSIONING_SHORT_PRESS == sGPDData.u8ButtonCount ) &&
(!(sGPDPersistentData.b8CommissioiningStatusBits & GPD_DE_COMM_MODE_SET_BIT)))
{
/* Button pressed till de commissioning count, send
* de commissioning command */
sGPDPersistentData.b8CommissioiningStatusBits =
sGPDPersistentData.b8CommissioiningStatusBits | GPD_DE_COMM_MODE_SET_BIT;
}
else if((CLEAR_PERSISTENT_SHORT_PRESS == sGPDData.u8ButtonCount ) &&
(sGPDPersistentData.b8CommissioiningStatusBits & GPD_DE_COMM_MODE_SET_BIT))
{
/* Button pressed till factory reset, clear persistent data */
vClearPersistentData(TRUE);
sGPDData.u8ButtonCount = 0;
vREG_SysWrite(REG_SYS_WK_T1, sGPDData.u8ButtonCount);
return;
}
else if((1 == sGPDData.u8ButtonCount ) &&
((sGPDPersistentData.b8CommissioiningStatusBits & GPD_DE_COMM_MODE_SET_BIT)))
{
sGPDPersistentData.b8CommissioiningStatusBits &= ~GPD_DE_COMM_MODE_SET_BIT;
}
else if(sGPDData.u8ButtonCount > CLEAR_PERSISTENT_SHORT_PRESS)
{
sGPDData.u8ButtonCount = 0;
}
if(sGPDPersistentData.b8CommissioiningStatusBits & GPD_DE_COMM_MODE_SET_BIT)
{
sGPDData.u8ButtonCount++;
vSendDecommissioingCmd();
}
else
#endif
{
DBG_vPrintf(DBG_DEVICE_SWITCH, "\n Sending operational command \n" );
/* send operational command here */
#if (GPD_TYPE == GP_LEVEL_CONTROL_SWITCH)
if(u8CmdId)
{
/* specific command */
GPD_SendSpecificCommand(u8CmdId);
sGPDData.u8ButtonCount = 0x00;
}
else
#endif
{
/* default command */
sGPDData.u8ButtonCount++;
GPD_SendOperationalCommand();
}
/* required to update sequence number or frame control in persistent memory */
}
}
/*---------------------------------------------------------------------------*/
static int
init(void)
{
int put_index;
tsExtAddr node_long_address;
uint16_t node_short_address;
tx_in_progress = 0;
u32JPT_Init();
vMMAC_Enable();
/* Enable/disable interrupts */
if(poll_mode) {
vMMAC_EnableInterrupts(NULL);
vMMAC_ConfigureInterruptSources(0);
} else {
vMMAC_EnableInterrupts(&radio_interrupt_handler);
} vMMAC_ConfigureRadio();
set_channel(MICROMAC_CONF_CHANNEL);
set_txpower(MICROMAC_CONF_TX_POWER);
vMMAC_GetMacAddress(&node_long_address);
/* Short addresses are disabled by default */
node_short_address = (uint16_t)node_long_address.u32L;
vMMAC_SetRxAddress(frame802154_get_pan_id(), node_short_address, &node_long_address);
/* Disable hardware backoff */
vMMAC_SetTxParameters(1, 0, 0, 0);
vMMAC_SetCutOffTimer(0, FALSE);
/* Initialize ring buffer and first input packet pointer */
ringbufindex_init(&input_ringbuf, MIRCOMAC_CONF_BUF_NUM);
/* get pointer to next input slot */
put_index = ringbufindex_peek_put(&input_ringbuf);
if(put_index == -1) {
rx_frame_buffer = NULL;
printf("micromac_radio init:! no buffer available. Abort init.\n");
off();
return 0;
} else {
rx_frame_buffer = &input_array[put_index];
}
input_frame_buffer = rx_frame_buffer;
process_start(µmac_radio_process, NULL);
#if RADIO_TEST_MODE == RADIO_TEST_MODE_HIGH_PWR
/* Enable high power mode.
* In this mode DIO2 goes high during RX
* and DIO3 goes high during TX
**/
vREG_SysWrite(REG_SYS_PWR_CTRL,
u32REG_SysRead(REG_SYS_PWR_CTRL)
| REG_SYSCTRL_PWRCTRL_RFRXEN_MASK
| REG_SYSCTRL_PWRCTRL_RFTXEN_MASK);
#elif RADIO_TEST_MODE == RADIO_TEST_MODE_ADVANCED
/* output internal radio status on IO pins.
* See Chris@NXP email */
vREG_SysWrite(REG_SYS_PWR_CTRL,
u32REG_SysRead(REG_SYS_PWR_CTRL) | (1UL << 26UL));
#endif /* TEST_MODE */
return 1;
}
