static void tegra_adma_start(struct tegra_adma_chan *tdc) { struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc); struct tegra_adma_chan_regs *ch_regs; struct tegra_adma_desc *desc; if (!vd) return; list_del(&vd->node); desc = to_tegra_adma_desc(&vd->tx); if (!desc) { dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n"); return; } ch_regs = &desc->ch_regs; tdc->tx_buf_pos = 0; tdc->tx_buf_count = 0; tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc); tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr); tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr); tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl); tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config); /* Start ADMA */ tdma_ch_write(tdc, ADMA_CH_CMD, 1); tdc->desc = desc; }
static void hsu_dma_start_transfer(struct hsu_dma_chan *hsuc) { struct virt_dma_desc *vdesc; /* Get the next descriptor */ vdesc = vchan_next_desc(&hsuc->vchan); if (!vdesc) { hsuc->desc = NULL; return; } list_del(&vdesc->node); hsuc->desc = to_hsu_dma_desc(vdesc); /* Start the channel with a new descriptor */ hsu_dma_start_channel(hsuc); }
static void st_fdma_xfer_desc(struct st_fdma_chan *fchan) { struct virt_dma_desc *vdesc; unsigned long nbytes, ch_cmd, cmd; vdesc = vchan_next_desc(&fchan->vchan); if (!vdesc) return; fchan->fdesc = to_st_fdma_desc(vdesc); nbytes = fchan->fdesc->node[0].desc->nbytes; cmd = FDMA_CMD_START(fchan->vchan.chan.chan_id); ch_cmd = fchan->fdesc->node[0].pdesc | FDMA_CH_CMD_STA_START; /* start the channel for the descriptor */ fnode_write(fchan, nbytes, FDMA_CNTN_OFST); fchan_write(fchan, ch_cmd, FDMA_CH_CMD_OFST); writel(cmd, fchan->fdev->slim_rproc->peri + FDMA_CMD_SET_OFST); dev_dbg(fchan->fdev->dev, "start chan:%d\n", fchan->vchan.chan.chan_id); }