u32 stbuf_space(struct stream_buf_s *buf) { /* reserved space for safe write, the parser fifo size is 1024byts, so reserve it */ int size; #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 if (HAS_HEVC_VDEC && buf->type == BUF_TYPE_HEVC) size = buf->canusebuf_size - READ_VREG(HEVC_STREAM_LEVEL); else #endif size = (buf->canusebuf_size - _READ_ST_REG(LEVEL)) ; #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD if ((buf->type == BUF_TYPE_VIDEO) && (vdec_on(VDEC_2))) { if ((_READ_VDEC2_ST_REG(START_PTR) == _READ_ST_REG(START_PTR)) && (_READ_VDEC2_ST_REG(END_PTR) == _READ_ST_REG(END_PTR)) && (_READ_VDEC2_ST_REG(CONTROL) & MEM_CTRL_FILL_EN)) { size = min(size, (int)(buf->canusebuf_size - _READ_VDEC2_ST_REG(LEVEL))); } } #endif if(buf->canusebuf_size>=buf->buf_size/2) size=size-6*1024;//old reversed value,tobe full, reversed only... if ((buf->type == BUF_TYPE_VIDEO) || (HAS_HEVC_VDEC && buf->type == BUF_TYPE_HEVC)) { size -= READ_MPEG_REG(PARSER_VIDEO_HOLE); } return size > 0 ? size : 0; }
static void amhevc_pg_enable(bool enable) { #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 if (HAS_HEVC_VDEC) { ulong timeout; if(!vdec_on(VDEC_HEVC)) return; if (enable) { // WRITE_VREG(VDEC2_GCLK_EN, 0x3ff); } else { timeout = jiffies + HZ / 10; while (READ_VREG(HEVC_MDEC_PIC_DC_STATUS) != 0) { if (time_after(jiffies, timeout)) { WRITE_VREG_BITS(HEVC_MDEC_PIC_DC_CTRL, 1, 0, 1); WRITE_VREG_BITS(HEVC_MDEC_PIC_DC_CTRL, 0, 0, 1); READ_VREG(HEVC_MDEC_PIC_DC_STATUS); READ_VREG(HEVC_MDEC_PIC_DC_STATUS); READ_VREG(HEVC_MDEC_PIC_DC_STATUS); break; } } timeout = jiffies + HZ / 10; while (READ_VREG(HEVC_DBLK_STATUS) & 1) { if (time_after(jiffies, timeout)) { WRITE_VREG(HEVC_DBLK_CTRL, 3); WRITE_VREG(HEVC_DBLK_CTRL, 0); READ_VREG(HEVC_DBLK_STATUS); READ_VREG(HEVC_DBLK_STATUS); READ_VREG(HEVC_DBLK_STATUS); break; } } timeout = jiffies + HZ / 10; while (READ_VREG(HEVC_DCAC_DMA_CTRL) & 0x8000) { if (time_after(jiffies, timeout)) { break; } } } } #endif }
static void amvdec2_pg_enable(bool enable) { if (HAS_VDEC2) { ulong timeout; if(!vdec_on(VDEC_2)) return; if (enable) { // WRITE_VREG(VDEC2_GCLK_EN, 0x3ff); } else { timeout = jiffies + HZ / 10; while (READ_VREG(VDEC2_MDEC_PIC_DC_STATUS) != 0) { if (time_after(jiffies, timeout)) { WRITE_VREG_BITS(VDEC2_MDEC_PIC_DC_CTRL, 1, 0, 1); WRITE_VREG_BITS(VDEC2_MDEC_PIC_DC_CTRL, 0, 0, 1); READ_VREG(VDEC2_MDEC_PIC_DC_STATUS); READ_VREG(VDEC2_MDEC_PIC_DC_STATUS); READ_VREG(VDEC2_MDEC_PIC_DC_STATUS); break; } } timeout = jiffies + HZ / 10; while (READ_VREG(VDEC2_DBLK_STATUS) & 1) { if (time_after(jiffies, timeout)) { WRITE_VREG(VDEC2_DBLK_CTRL, 3); WRITE_VREG(VDEC2_DBLK_CTRL, 0); READ_VREG(VDEC2_DBLK_STATUS); READ_VREG(VDEC2_DBLK_STATUS); READ_VREG(VDEC2_DBLK_STATUS); break; } } timeout = jiffies + HZ / 10; while (READ_VREG(VDEC2_DCAC_DMA_CTRL) & 0x8000) { if (time_after(jiffies, timeout)) { break; } } } } }
static void amhevc_pg_enable(bool enable) { if (has_hevc_vdec()) { ulong timeout; if (!vdec_on(VDEC_HEVC)) return; if (enable) { /* WRITE_VREG(VDEC2_GCLK_EN, 0x3ff); */ } else { timeout = jiffies + HZ / 10; while (READ_VREG(HEVC_MDEC_PIC_DC_STATUS) != 0) { if (time_after(jiffies, timeout)) { WRITE_VREG_BITS(HEVC_MDEC_PIC_DC_CTRL, 1, 0, 1); WRITE_VREG_BITS(HEVC_MDEC_PIC_DC_CTRL, 0, 0, 1); READ_VREG(HEVC_MDEC_PIC_DC_STATUS); READ_VREG(HEVC_MDEC_PIC_DC_STATUS); READ_VREG(HEVC_MDEC_PIC_DC_STATUS); break; } } timeout = jiffies + HZ / 10; while (READ_VREG(HEVC_DBLK_STATUS) & 1) { if (time_after(jiffies, timeout)) { WRITE_VREG(HEVC_DBLK_CTRL, 3); WRITE_VREG(HEVC_DBLK_CTRL, 0); READ_VREG(HEVC_DBLK_STATUS); READ_VREG(HEVC_DBLK_STATUS); READ_VREG(HEVC_DBLK_STATUS); break; } } timeout = jiffies + HZ / 10; while (READ_VREG(HEVC_DCAC_DMA_CTRL) & 0x8000) { if (time_after(jiffies, timeout)) break; } } } }
static int vdec_is_paused(void) { static unsigned long old_wp = -1, old_rp = -1, old_level = -1; unsigned long wp, rp, level; static int paused_time = 0; #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 if (HAS_HEVC_VDEC) { if ((vdec_on(VDEC_HEVC)) && (READ_VREG(HEVC_STREAM_CONTROL) & 1)) { wp = READ_VREG(HEVC_STREAM_WR_PTR); rp = READ_VREG(HEVC_STREAM_RD_PTR); level = READ_VREG(HEVC_STREAM_LEVEL); } else { wp = READ_VREG(VLD_MEM_VIFIFO_WP); rp = READ_VREG(VLD_MEM_VIFIFO_RP); level = READ_VREG(VLD_MEM_VIFIFO_LEVEL); } } else #endif { wp = READ_VREG(VLD_MEM_VIFIFO_WP); rp = READ_VREG(VLD_MEM_VIFIFO_RP); level = READ_VREG(VLD_MEM_VIFIFO_LEVEL); } if ((rp == old_rp && level > 1024) || /*have data,but output buffer is full */ (rp == old_rp && wp == old_wp && level == level)) { /*no write && not read*/ paused_time++; } else { paused_time = 0; } old_wp = wp; old_rp = rp; old_level = level; if (paused_time > 10) { return 1; } return 0; }