static void set_secondary_clock_state(u8 state) { u8 value; switch (state) { case VIA_STATE_ON: value = 0x80; break; case VIA_STATE_OFF: value = 0x00; break; default: return; } via_write_reg_mask(VIASR, 0x1B, value, 0xC0); }
static void set_engine_pll_state(u8 state) { u8 value; switch (state) { case VIA_STATE_ON: value = 0x02; break; case VIA_STATE_OFF: value = 0x00; break; default: return; } via_write_reg_mask(VIASR, 0x2D, value, 0x03); }
static void set_secondary_clock_source(enum via_clksrc source, bool use_pll) { u8 data = set_clock_source_common(source, use_pll); via_write_reg_mask(VIACR, 0x6C, data, 0x0F); }
static void set_primary_clock_source(enum via_clksrc source, bool use_pll) { u8 data = set_clock_source_common(source, use_pll) << 4; via_write_reg_mask(VIACR, 0x6C, data, 0xF0); }