void up_decodeirq(uint32_t *regs)
{
vic_vector_t vector = (vic_vector_t) vic_getreg(VIC_ADDRESS_OFFSET);
/* Acknowledge the interrupt */
up_ack_irq(irq);
/* Valid Interrupt */
if (vector != NULL)
{
(vector)(regs);
}
}
void up_enable_irq(int irq)
{
/* Verify that the IRQ number is within range */
if (irq < NR_IRQS)
{
/* Disable all interrupts */
irqstate_t flags = irqsave();
/* Enable the irq by setting the corresponding bit in the VIC Interrupt
* Enable register.
*/
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);
vic_putreg(val | (1 << irq), VIC_INTENABLE_OFFSET);
irqrestore(flags);
}
}
void up_maskack_irq(int irq)
{
uint32_t reg32;
if ((unsigned)irq < NR_IRQS)
{
/* Mask the IRQ by clearing the associated bit in Software Priority Mask
* register
*/
reg32 = vic_getreg(VIC_PRIORITY_MASK_OFFSET);
reg32 &= ~(1 << irq);
vic_putreg(reg32, VIC_PRIORITY_MASK_OFFSET);
}
/* Clear interrupt */
vic_putreg((1 << irq), VIC_SOFTINTCLEAR_OFFSET);
#ifdef CONFIG_VECTORED_INTERRUPTS
vic_putreg(0, VIC_ADDRESS_OFFSET); /* dummy write to clear VICADDRESS */
#endif
}
void up_decodeirq(uint32_t *regs)
{
vic_vector_t vector = (vic_vector_t)vic_getreg(LPC214X_VIC_VECTADDR_OFFSET);
vector(regs);
}
