static int tegra_lcd_probe(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct tegra_lcd_priv *priv = dev_get_priv(dev); const void *blob = gd->fdt_blob; int type = DCACHE_OFF; /* Initialize the Tegra display controller */ if (tegra_display_probe(blob, priv, (void *)plat->base)) { printf("%s: Failed to probe display driver\n", __func__); return -1; } tegra_lcd_check_next_stage(blob, priv, 1); /* Set up the LCD caching as requested */ if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH) type = DCACHE_WRITETHROUGH; else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK) type = DCACHE_WRITEBACK; mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type); /* Enable flushing after LCD writes if requested */ video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH); uc_priv->xsize = priv->width; uc_priv->ysize = priv->height; uc_priv->bpix = priv->log2_bpp; debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer, plat->size); return 0; }
static int simple_video_probe(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); const void *blob = gd->fdt_blob; const int node = dev_of_offset(dev); const char *format; fdt_addr_t base; fdt_size_t size; base = fdtdec_get_addr_size_auto_parent(blob, dev_of_offset(dev->parent), node, "reg", 0, &size, false); if (base == FDT_ADDR_T_NONE) { debug("%s: Failed to decode memory region\n", __func__); return -EINVAL; } debug("%s: base=%llx, size=%llu\n", __func__, base, size); /* * TODO is there some way to reserve the framebuffer * region so it isn't clobbered? */ plat->base = base; plat->size = size; video_set_flush_dcache(dev, true); debug("%s: Query resolution...\n", __func__); uc_priv->xsize = fdtdec_get_uint(blob, node, "width", 0); uc_priv->ysize = fdtdec_get_uint(blob, node, "height", 0); uc_priv->rot = 0; format = fdt_getprop(blob, node, "format", NULL); debug("%s: %dx%d@%s\n", __func__, uc_priv->xsize, uc_priv->ysize, format); if (strcmp(format, "r5g6b5") == 0) { uc_priv->bpix = VIDEO_BPP16; } else if (strcmp(format, "a8b8g8r8") == 0) { uc_priv->bpix = VIDEO_BPP32; } else { printf("%s: invalid format: %s\n", __func__, format); return -EINVAL; } return 0; }
static int atmel_hlcdc_probe(struct udevice *dev) { struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct atmel_hlcdc_priv *priv = dev_get_priv(dev); int ret; ret = at91_hlcdc_enable_clk(dev); if (ret) return ret; atmel_hlcdc_init(dev); uc_priv->xsize = priv->timing.hactive.typ; uc_priv->ysize = priv->timing.vactive.typ; uc_priv->bpix = priv->vl_bpix; /* Enable flushing if we enabled dcache */ video_set_flush_dcache(dev, true); return 0; }
static int tegra124_lcd_init(struct udevice *dev, void *lcdbase, enum video_log2_bpp l2bpp) { struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct display_timing timing; int ret; clock_set_up_plldp(); clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000); clock_enable(PERIPH_ID_HOST1X); clock_enable(PERIPH_ID_DISP1); clock_enable(PERIPH_ID_PWM); clock_enable(PERIPH_ID_DPAUX); clock_enable(PERIPH_ID_SOR0); udelay(2); reset_set_enable(PERIPH_ID_HOST1X, 0); reset_set_enable(PERIPH_ID_DISP1, 0); reset_set_enable(PERIPH_ID_PWM, 0); reset_set_enable(PERIPH_ID_DPAUX, 0); reset_set_enable(PERIPH_ID_SOR0, 0); ret = display_init(dev, lcdbase, 1 << l2bpp, &timing); if (ret) return ret; uc_priv->xsize = roundup(timing.hactive.typ, 16); uc_priv->ysize = timing.vactive.typ; uc_priv->bpix = l2bpp; video_set_flush_dcache(dev, 1); debug("%s: done\n", __func__); return 0; }