/*
* pci_pos_write()
*/
static void pci_pos_write(cpu_gen_t *cpu,struct pci_device *dev,
int reg,m_uint32_t value)
{
struct pos_oc3_data *d = dev->priv_data;
#if DEBUG_ACCESS
POS_LOG(d,"write 0x%x to PCI register 0x%x\n",value,reg);
#endif
switch(reg) {
case PCI_REG_BAR0:
vm_map_device(cpu->vm,&d->dev,(m_uint64_t)value);
POS_LOG(d,"registers are mapped at 0x%x\n",value);
break;
}
}
/*
* dev_mv64460_access()
*/
void *dev_mv64460_access(cpu_gen_t *cpu,struct vdevice *dev,m_uint32_t offset,
u_int op_size,u_int op_type,m_uint64_t *data)
{
struct mv64460_data *mv_data = dev->priv_data;
MV64460_LOCK(mv_data);
if (op_type == MTS_READ) {
*data = 0;
} else {
if (op_size == 4)
*data = swap32(*data);
}
#if DEBUG_ACCESS
if (op_type == MTS_READ) {
cpu_log(cpu,"MV64460",
"read access to register 0x%x, pc=0x%llx\n",
offset,cpu_get_pc(cpu));
} else {
cpu_log(cpu,"MV64460",
"write access to register 0x%x, value=0x%llx, pc=0x%llx\n",
offset,*data,cpu_get_pc(cpu));
}
#endif
/* Serial DMA channel registers */
if (mv64460_sdma_access(cpu,dev,offset,op_size,op_type,data) != 0)
goto done;
/* MPSC registers */
if (mv64460_mpsc_access(cpu,dev,offset,op_size,op_type,data) != 0)
goto done;
switch(offset) {
/* Interrupt Main Cause Low */
case MV64460_REG_ILMCR:
if (op_type == MTS_READ)
*data = mv_data->intr_lo;
break;
/* Interrupt Main Cause High */
case MV64460_REG_IHMCR:
if (op_type == MTS_READ)
*data = mv_data->intr_hi;
break;
/* CPU_INTn[0] Mask Low */
case MV64460_REG_CPU_INTN0_MASK_LO:
if (op_type == MTS_READ) {
*data = mv_data->cpu_intn0_mask_lo;
} else {
mv_data->cpu_intn0_mask_lo = *data;
mv64460_int_sync(mv_data);
}
break;
/* CPU_INTn[0] Mask High */
case MV64460_REG_CPU_INTN0_MASK_HI:
if (op_type == MTS_READ) {
*data = mv_data->cpu_intn0_mask_hi;
} else {
mv_data->cpu_intn0_mask_hi = *data;
mv64460_int_sync(mv_data);
}
break;
/* CPU_INTn[0] Select Cause (read-only) */
case MV64460_REG_CPU_INTN0_SEL_CAUSE:
if (op_type == MTS_READ) {
*data = mv64460_ic_get_sel_cause(mv_data,
mv_data->cpu_intn0_mask_lo,
mv_data->cpu_intn0_mask_hi);
}
break;
/* CPU_INTn[1] Mask Low */
case MV64460_REG_CPU_INTN1_MASK_LO:
if (op_type == MTS_READ)
*data = mv_data->cpu_intn1_mask_lo;
else
mv_data->cpu_intn1_mask_lo = *data;
break;
/* CPU_INTn[1] Mask High */
case MV64460_REG_CPU_INTN1_MASK_HI:
if (op_type == MTS_READ)
*data = mv_data->cpu_intn1_mask_hi;
else
mv_data->cpu_intn1_mask_hi = *data;
break;
/* CPU_INTn[1] Select Cause (read-only) */
case MV64460_REG_CPU_INTN1_SEL_CAUSE:
if (op_type == MTS_READ) {
*data = mv64460_ic_get_sel_cause(mv_data,
mv_data->cpu_intn1_mask_lo,
mv_data->cpu_intn1_mask_hi);
}
break;
/* INT0n Mask Low */
case MV64460_REG_INT0N_MASK_LO:
if (op_type == MTS_READ)
*data = mv_data->int0n_mask_lo;
else
mv_data->int0n_mask_lo = *data;
break;
/* INT0n Mask High */
case MV64460_REG_INT0N_MASK_HI:
if (op_type == MTS_READ)
*data = mv_data->int0n_mask_hi;
else
mv_data->int0n_mask_hi = *data;
break;
/* INT0n Select Cause (read-only) */
case MV64460_REG_INT0N_SEL_CAUSE:
if (op_type == MTS_READ) {
*data = mv64460_ic_get_sel_cause(mv_data,
mv_data->int0n_mask_lo,
mv_data->int0n_mask_hi);
}
break;
/* INT1n Mask Low */
case MV64460_REG_INT1N_MASK_LO:
if (op_type == MTS_READ)
*data = mv_data->int1n_mask_lo;
else
mv_data->int1n_mask_lo = *data;
break;
/* INT1n Mask High */
case MV64460_REG_INT1N_MASK_HI:
if (op_type == MTS_READ)
*data = mv_data->int1n_mask_hi;
else
mv_data->int1n_mask_hi = *data;
break;
/* INT1n Select Cause (read-only) */
case MV64460_REG_INT1N_SEL_CAUSE:
if (op_type == MTS_READ) {
*data = mv64460_ic_get_sel_cause(mv_data,
mv_data->int1n_mask_lo,
mv_data->int1n_mask_hi);
}
break;
/* ===== PCI Bus 0 ===== */
case PCI_BUS_ADDR: /* pci configuration address (0xcf8) */
pci_dev_addr_handler(cpu,mv_data->bus[0],op_type,FALSE,data);
break;
case PCI_BUS_DATA: /* pci data address (0xcfc) */
pci_dev_data_handler(cpu,mv_data->bus[0],op_type,FALSE,data);
break;
/* ===== PCI Bus 0 ===== */
case 0xc78: /* pci configuration address (0xc78) */
pci_dev_addr_handler(cpu,mv_data->bus[1],op_type,FALSE,data);
break;
case 0xc7c: /* pci data address (0xc7c) */
pci_dev_data_handler(cpu,mv_data->bus[1],op_type,FALSE,data);
break;
/* MII */
case 0x2004:
if (op_type == MTS_READ)
*data = 0x08000000;
break;
/* GPP interrupt cause */
case MV64460_REG_GPP_INTR_CAUSE:
if (op_type == MTS_READ)
*data = mv_data->gpp_intr;
break;
/* GPP interrupt mask0 */
case MV64460_REG_GPP_INTR_MASK0:
if (op_type == MTS_READ) {
*data = mv_data->gpp_mask0;
} else {
mv_data->gpp_mask0 = *data;
mv64460_gpio_update_int_status(mv_data);
}
break;
/* GPP interrupt mask1 */
case MV64460_REG_GPP_INTR_MASK1:
if (op_type == MTS_READ) {
*data = mv_data->gpp_mask1;
} else {
mv_data->gpp_mask1 = *data;
mv64460_gpio_update_int_status(mv_data);
}
break;
/* GPP value set */
case MV64460_REG_GPP_VALUE_SET:
if (op_type == MTS_WRITE) {
mv_data->gpp_intr |= *data;
mv64460_gpio_update_int_status(mv_data);
}
break;
/* GPP value clear */
case MV64460_REG_GPP_VALUE_CLEAR:
if (op_type == MTS_WRITE) {
mv_data->gpp_intr &= ~(*data);
mv64460_gpio_update_int_status(mv_data);
}
break;
/* SDMA cause register */
case MV64460_REG_SDMA_CAUSE:
if (op_type == MTS_READ) {
*data = mv_data->sdma_cause;
} else {
mv_data->sdma_cause = *data;
mv64460_sdma_update_int_status(mv_data);
}
break;
/* SDMA mask register */
case MV64460_REG_SDMA_MASK:
if (op_type == MTS_READ) {
*data = mv_data->sdma_mask;
} else {
mv_data->sdma_mask = *data;
mv64460_sdma_update_int_status(mv_data);
}
break;
/* Integrated SRAM base address */
case MV64460_REG_SRAM_BASE:
if (op_type == MTS_READ) {
*data = mv_data->sram_dev.phys_addr << MV64460_SRAM_WIDTH;
} else {
m_uint64_t sram_addr;
sram_addr = *data & MV64460_SRAM_BASE_MASK;
sram_addr >>= MV64460_SRAM_BASE_SHIFT;
sram_addr <<= MV64460_SRAM_WIDTH;
vm_map_device(mv_data->vm,&mv_data->sram_dev,sram_addr);
MV64460_LOG(mv_data,"SRAM mapped at 0x%10.10llx\n",
mv_data->sram_dev.phys_addr);
}
break;
#if DEBUG_UNKNOWN
default:
if (op_type == MTS_READ) {
cpu_log(cpu,"MV64460","read from addr 0x%x, pc=0x%llx\n",
offset,cpu_get_pc(cpu));
} else {
cpu_log(cpu,"MV64460","write to addr 0x%x, value=0x%llx, "
"pc=0x%llx\n",offset,*data,cpu_get_pc(cpu));
}
#endif
}
done:
MV64460_UNLOCK(mv_data);
if ((op_type == MTS_READ) && (op_size == 4))
*data = swap32(*data);
return NULL;
}
