static int __init generic_timer_clocksource_init(struct vmm_devtree_node *node) { struct vmm_clocksource *cs; generic_timer_get_freq(node); if (generic_timer_hz == 0) { return VMM_EFAIL; } cs = vmm_zalloc(sizeof(struct vmm_clocksource)); if (!cs) { return VMM_EFAIL; } cs->name = "gen-timer"; cs->rating = 400; cs->read = &generic_counter_read; cs->mask = VMM_CLOCKSOURCE_MASK(56); vmm_clocks_calc_mult_shift(&cs->mult, &cs->shift, generic_timer_hz, VMM_NSEC_PER_SEC, 10); generic_timer_mult = cs->mult; generic_timer_shift = cs->shift; cs->priv = NULL; return vmm_clocksource_register(cs); }
int __init omap3_gpt_clocksource_init(u32 gpt_num, physical_addr_t prm_pa) { int rc; struct omap3_gpt_clocksource *cs; if ((rc = omap3_gpt_instance_init(gpt_num, prm_pa, NULL))) { return rc; } omap3_gpt_continuous(gpt_num); cs = vmm_zalloc(sizeof(struct omap3_gpt_clocksource)); if (!cs) { return VMM_EFAIL; } cs->gpt_num = gpt_num; cs->clksrc.name = omap3_gpt_config[gpt_num].name; cs->clksrc.rating = 200; cs->clksrc.read = &omap3_gpt_clocksource_read; cs->clksrc.mask = 0xFFFFFFFF; cs->clksrc.mult = vmm_clocksource_khz2mult((omap3_gpt_config[gpt_num].clk_hz)/1000, 24); cs->clksrc.shift = 24; cs->clksrc.priv = cs; return vmm_clocksource_register(&cs->clksrc); }
int __init epit_clocksource_init(void) { int rc = VMM_ENODEV; u32 clock; struct vmm_devtree_node *node; struct epit_clocksource *ecs; /* find a epit compatible node */ node = vmm_devtree_find_compatible(NULL, NULL, "freescale,epit-timer"); if (!node) { goto fail; } /* Read clock frequency from node */ rc = vmm_devtree_clock_frequency(node, &clock); if (rc) { goto fail; } /* allocate our struct */ ecs = vmm_zalloc(sizeof(struct epit_clocksource)); if (!ecs) { rc = VMM_ENOMEM; goto fail; } /* Map timer registers */ rc = vmm_devtree_regmap(node, &ecs->base, 0); if (rc) { goto regmap_fail; } /* Setup clocksource */ ecs->clksrc.name = node->name; ecs->clksrc.rating = 300; ecs->clksrc.read = epit_clksrc_read; ecs->clksrc.mask = VMM_CLOCKSOURCE_MASK(32); vmm_clocks_calc_mult_shift(&ecs->clksrc.mult, &ecs->clksrc.shift, clock, VMM_NSEC_PER_SEC, 10); ecs->clksrc.priv = ecs; /* Register clocksource */ rc = vmm_clocksource_register(&ecs->clksrc); if (rc) { goto register_fail; } return VMM_OK; register_fail: vmm_devtree_regunmap(node, ecs->base, 0); regmap_fail: vmm_free(ecs); fail: return rc; }
int arch_clocksource_init(void) { int rc; /* Register clocksource */ hpet_cs.mult = vmm_clocksource_khz2mult(1000, 20); if ((rc = vmm_clocksource_register(&hpet_cs))) { return rc; } return VMM_OK; }
int __init generic_timer_clocksource_init(void) { int rc; struct vmm_clocksource *cs; struct vmm_devtree_node *node; node = vmm_devtree_find_matching(NULL, generic_timer_match); if (!node) { return VMM_ENODEV; } if (generic_timer_hz == 0) { rc = vmm_devtree_clock_frequency(node, &generic_timer_hz); if (rc) { /* Use preconfigured counter frequency * in absence of dts node */ generic_timer_hz = generic_timer_reg_read(GENERIC_TIMER_REG_FREQ); } else { if (generic_timer_freq_writeable()) { /* Program the counter frequency * as per the dts node */ generic_timer_reg_write(GENERIC_TIMER_REG_FREQ, generic_timer_hz); } } } if (generic_timer_hz == 0) { return VMM_EFAIL; } cs = vmm_zalloc(sizeof(struct vmm_clocksource)); if (!cs) { return VMM_EFAIL; } cs->name = "gen-timer"; cs->rating = 400; cs->read = &generic_counter_read; cs->mask = VMM_CLOCKSOURCE_MASK(56); vmm_clocks_calc_mult_shift(&cs->mult, &cs->shift, generic_timer_hz, VMM_NSEC_PER_SEC, 10); cs->priv = NULL; return vmm_clocksource_register(cs); }
int __init omap3_s32k_clocksource_init(void) { int rc; /* Initialize omap3 s32k timer HW */ if ((rc = omap3_s32k_init())) { return rc; } /* Register clocksource */ s32k_clksrc.mult = vmm_clocksource_hz2mult(OMAP3_S32K_FREQ_HZ, 15); if ((rc = vmm_clocksource_register(&s32k_clksrc))) { return rc; } return VMM_OK; }
static int __init bcm2835_clocksource_init(struct vmm_devtree_node *node) { int rc; u32 clock; struct bcm2835_clocksource *bcs; /* Read clock frequency */ rc = vmm_devtree_clock_frequency(node, &clock); if (rc) { return rc; } bcs = vmm_zalloc(sizeof(struct bcm2835_clocksource)); if (!bcs) { return VMM_ENOMEM; } /* Map timer registers */ rc = vmm_devtree_regmap(node, &bcs->base, 0); if (rc) { vmm_free(bcs); return rc; } bcs->system_clock = (void *)(bcs->base + REG_COUNTER_LO); /* Setup clocksource */ bcs->clksrc.name = "bcm2835_timer"; bcs->clksrc.rating = 300; bcs->clksrc.read = bcm2835_clksrc_read; bcs->clksrc.mask = VMM_CLOCKSOURCE_MASK(32); vmm_clocks_calc_mult_shift(&bcs->clksrc.mult, &bcs->clksrc.shift, clock, VMM_NSEC_PER_SEC, 10); bcs->clksrc.priv = bcs; /* Register clocksource */ rc = vmm_clocksource_register(&bcs->clksrc); if (rc) { vmm_devtree_regunmap(node, bcs->base, 0); vmm_free(bcs); return rc; } return VMM_OK; }
int __init s32k_clocksource_init(physical_addr_t base) { int rc; virtual_addr_t synct_base; /* Map registers */ synct_base = vmm_host_iomap(base, 0x1000); /* Save pointer to registers in clocksource private */ s32k_clksrc.priv = (void *)synct_base; /* Compute mult for clocksource */ vmm_clocks_calc_mult_shift(&s32k_clksrc.mult, &s32k_clksrc.shift, S32K_FREQ_HZ, VMM_NSEC_PER_SEC, 10); /* Register clocksource */ if ((rc = vmm_clocksource_register(&s32k_clksrc))) { return rc; } return VMM_OK; }