static void set_tcon_lvds(Lcd_Config_t *pConf)
{
vpp_set_matrix_ycbcr2rgb(2, 0);
aml_write_reg32(P_ENCL_VIDEO_RGBIN_CTRL, 3);
aml_write_reg32(P_L_RGB_BASE_ADDR, 0);
aml_write_reg32(P_L_RGB_COEFF_ADDR, 0x400);
if (pConf->lcd_basic.lcd_bits == 8)
aml_write_reg32(P_L_DITH_CNTL_ADDR, 0x400);
else if (pConf->lcd_basic.lcd_bits == 6)
aml_write_reg32(P_L_DITH_CNTL_ADDR, 0x600);
else
aml_write_reg32(P_L_DITH_CNTL_ADDR, 0);
aml_write_reg32(P_VPP_MISC, aml_read_reg32(P_VPP_MISC) & ~(VPP_OUT_SATURATE));
}
static void set_tcon_vbyone(Lcd_Config_t *pConf)
{
//Lcd_Timing_t *tcon_adr = &(pConf->lcd_timing);
vpp_set_matrix_ycbcr2rgb(2, 0);
aml_write_reg32(P_ENCL_VIDEO_RGBIN_CTRL, 3);
aml_write_reg32(P_L_RGB_BASE_ADDR, 0);
aml_write_reg32(P_L_RGB_COEFF_ADDR, 0x400);
//aml_write_reg32(P_L_POL_CNTL_ADDR, 3)
//aml_write_reg32(P_L_DUAL_PORT_CNTL_ADDR, (0x1 << LCD_TTL_SEL));
// if(pConf->lcd_basic.lcd_bits == 8)
// aml_write_reg32(P_L_DITH_CNTL_ADDR, 0x400);
// else if(pConf->lcd_basic.lcd_bits == 6)
// aml_write_reg32(P_L_DITH_CNTL_ADDR, 0x600);
// else
// aml_write_reg32(P_L_DITH_CNTL_ADDR, 0);
//PRINT_INFO("final LVDS_FIFO_CLK = %d\n", clk_util_clk_msr(24));
//PRINT_INFO("final cts_encl_clk = %d\n", clk_util_clk_msr(9));
aml_write_reg32(P_VPP_MISC, aml_read_reg32(P_VPP_MISC) & ~(VPP_OUT_SATURATE));
}
static void init_lvds(void)
{
unsigned char lvds_bits_cfg = 1; // 0:10bits, 1:8bits, 2:6bits, 3:4bits.
unsigned int dithering_cfg = 0;
switch(lvds_bits) {
case 10:
lvds_bits_cfg = 0;
dithering_cfg = 0;
break;
case 8:
lvds_bits_cfg = 1;
dithering_cfg = 0x400;
break;
case 6:
lvds_bits_cfg = 2;
dithering_cfg = 0x600;
break;
case 4:
lvds_bits_cfg = 3;
dithering_cfg = 0;
break;
}
clk_util_lvds_set_clk_div( 2, // unsigned long divn_sel, // select divide by 3.5 (0 = div1, 1=divN,2 = div3.5)
7, // unsigned long divn_tcnt, // ignored
0 ); // unsigned long div2_en, // divide by 1 for LVDS
//Wr( REG_LVDS_PHY_CNTL0, 0xffff );
// wire fifo_en = tst_lvds_tmode ? atest_i[3] : gen_cntl[3];
// wire fifo_wr_bist_gate = tst_lvds_tmode ? 1'b1 : gen_cntl[2];
// wire [1:0] fifo_wr_mode = gen_cntl[1:0];
//Wr( LVDS_GEN_CNTL, (Rd(LVDS_GEN_CNTL) | (3 << 0)) ); //use dv_continuous as the fifo_wr_en
// enable the FIFO and use dv_continuous as the fifo_wr_en
Wr( LVDS_GEN_CNTL, (Rd(LVDS_GEN_CNTL) | (1 << 3) | (3<< 0)));
set_tv_enc_1080p();
vpp_set_matrix_ycbcr2rgb(2, 0);
Wr(ENCP_VIDEO_RGBIN_CTRL, 3);
Wr(RGB_BASE_ADDR, 0);
Wr(RGB_COEFF_ADDR, 0x400);
//Wr(ENCP_VIDEO_EN, 1);
Wr(LVDS_PACK_CNTL_ADDR,
( jeida? 0:1 ) | // repack
( port_reverse?(0<<2):(1<<2) ) | // odd_even reverse
( 0<<3 ) | // reserve
( 0<<4 ) | // lsb first
( 0<<5 ) | // pn swap
( 1<<6 ) | // dual port
( 0<<7 ) | // use tcon control
( lvds_bits_cfg<<8) | // 0:10bits, 1:8bits, 2:6bits, 3:4bits.
( 0<<10 ) | // 0:R, 1:G, 2:B, 3:0
( 1<<12 ) |
( 2<<14 ));
Wr(POL_CNTL_ADDR, (1 << DCLK_SEL) |
//(0x1 << HS_POL) |
(0x1 << VS_POL)
);
Wr(DITH_CNTL_ADDR, dithering_cfg);
}
