void govm_set_pip_color_format(vdo_color_fmt format)
{
switch (format) {
case VDO_COL_FMT_ARGB:
vppif_reg32_write(GOVM_PIP_COLFMT_RGB, 1);
break;
case VDO_COL_FMT_YUV444:
vppif_reg32_write(GOVM_PIP_COLFMT_RGB, 0);
vppif_reg32_write(GOVM_PIP_COLFMT_444, 1);
vppif_reg32_write(GOVM_PIP_COLFMT_422, 0);
break;
case VDO_COL_FMT_YUV422H:
vppif_reg32_write(GOVM_PIP_COLFMT_RGB, 0);
vppif_reg32_write(GOVM_PIP_COLFMT_444, 0);
vppif_reg32_write(GOVM_PIP_COLFMT_422, 0);
break;
case VDO_COL_FMT_YUV420:
vppif_reg32_write(GOVM_PIP_COLFMT_RGB, 0);
vppif_reg32_write(GOVM_PIP_COLFMT_444, 0);
vppif_reg32_write(GOVM_PIP_COLFMT_422, 1);
break;
default:
DPRINT("*E* check the parameter.\n");
return;
}
if( format == VDO_COL_FMT_ARGB ){
if( govw_get_hd_color_format() < VDO_COL_FMT_ARGB ){
DPRINT("*E* govw & pip color fmt not match");
}
}
else {
if( govw_get_hd_color_format() >= VDO_COL_FMT_ARGB ){
DPRINT("*E* govw & pip color fmt not match");
}
}
}
void lvds_init(void)
{
vppif_reg32_write(0xd8130254,BIT10,10,1); // LVDS clock enable
vppif_reg32_write(LVDS_REG_LEVEL,1);
vppif_reg32_write(LVDS_REG_UPDATE,1);
vppif_reg32_write(LVDS_PLL_R_F,0x1);
vppif_reg32_write(LVDS_PLL_CPSET,0x1);
// patch for A1
vppif_reg32_write(LVDS_TEST,0x2);
vppif_reg32_write(LVDS_LDI_SHIFT_LEFT,1);
}
void scl_set_H_scale(int A, int B)
{
unsigned int H_STEP;
unsigned int H_SUB_STEP;
unsigned int H_THR_DIV2;
// DBGMSG("vpu_set_H_scale(%d,%d)\r\n", A, B);
if( A > B ){
H_STEP = (B -1) * 16 / A;
H_SUB_STEP = (B -1) * 16 % A;
}
else {
H_STEP = (16 * B / A);
H_SUB_STEP = ((16 * B) % A);
}
H_THR_DIV2 = A;
// DBGMSG("H step %d,sub step %d, div2 %d\r\n", H_STEP, H_SUB_STEP, H_THR_DIV2);
vppif_reg32_write(SCL_HXWIDTH,((A>B)?A:B));
vppif_reg32_write(SCL_H_STEP, H_STEP);
vppif_reg32_write(SCL_H_SUBSTEP, H_SUB_STEP);
vppif_reg32_write(SCL_H_THR, H_THR_DIV2);
vppif_reg32_write(SCL_H_I_SUBSTEPCNT, 0);
}
void lvds_init(void)
{
vppif_reg32_write(LVDS_REG_LEVEL,1);
vppif_reg32_write(LVDS_REG_UPDATE,1);
vppif_reg32_write(LVDS_PLL_R_F,0x1);
vppif_reg32_write(LVDS_PLL_CPSET,0x1);
// patch for A1
vppif_reg32_write(LVDS_TEST,0x2);
vppif_reg32_write(LVDS_LDI_SHIFT_LEFT,1);
}
void scl_set_scale(unsigned int SRC_W,unsigned int SRC_H,unsigned int DST_W,unsigned int DST_H)
{
int h_scale_up;
int v_scale_up;
DBGMSG("[SCL] src(%dx%d),dst(%dx%d)\n",SRC_W,SRC_H,DST_W,DST_H);
h_scale_up = ( DST_W > SRC_W )? 1:0;
v_scale_up = ( DST_H > SRC_H )? 1:0;
if( ((DST_W / SRC_W) >= 32) || ((DST_W / SRC_W) < 1/32) ){
DBGMSG("*W* SCL H scale rate invalid\n");
}
if( ((DST_H / SRC_H) >= 32) || ((DST_H / SRC_H) < 1/32) ){
DBGMSG("*W* SCL V scale rate invalid\n");
}
// DBGMSG("scale H %d,V %d\n",h_scale_up,v_scale_up);
sclr_set_mif2_enable(VPP_FLAG_DISABLE);
scl_set_scale_PP(SRC_W,DST_W,1);
if( h_scale_up ){ // max 32
vppif_reg32_out(REG_SCL_HSCL_TB0,3);
vppif_reg32_out(REG_SCL_HPTR,0);
vppif_reg32_write(SCL_BILINEAR_H,0);
}
else { // min 1/32
vppif_reg32_out(REG_SCL_HSCL_TB0,1);
scl_set_scale_RT(SRC_W,DST_W,1);
}
scl_set_scale_PP(SRC_H,DST_H,0);
if( v_scale_up ){ // max 32
vppif_reg32_out(REG_SCL_VSCL_TB0,3);
vppif_reg32_out(REG_SCL_VPTR,0);
}
else { // min 1/16
scl_set_scale_RT(SRC_H,DST_H,0);
// mif2 enable in real quality mode,only mif1 in SCL recursive mode
if( vppif_reg32_read(SCL_TG_GOVWTG_ENABLE) && (vppif_reg32_read(SCL_SCLDW_METHOD)==0)){
sclr_set_mif2_enable(VPP_FLAG_ENABLE);
}
}
scl_set_scale_enable(v_scale_up, h_scale_up);
}
void sclw_set_fb_width(U32 width,U32 buf_width)
{
vppif_reg32_write(SCLW_YPXLWID, width);
vppif_reg32_write(SCLW_YBUFWID, buf_width);
if( sclw_get_color_format() == VDO_COL_FMT_YUV444 ){
vppif_reg32_write(SCLW_CPXLWID, width);
vppif_reg32_write(SCLW_CBUFWID, buf_width * 2);
}
else {
vppif_reg32_write(SCLW_CPXLWID, width / 2);
vppif_reg32_write(SCLW_CBUFWID, buf_width);
}
}
void scl_init(void *base)
{
vpu_mod_t *mod_p;
vpp_fb_base_t *fb_p;
mod_p = (vpu_mod_t *) base;
fb_p = mod_p->fb_p;
scl_set_reg_level(VPP_REG_LEVEL_1);
scl_set_tg_enable(VPP_FLAG_DISABLE);
scl_set_enable(VPP_FLAG_DISABLE);
scl_set_int_enable(VPP_FLAG_DISABLE, VPP_INT_ALL);
sclr_set_mif_enable(VPP_FLAG_DISABLE);
sclr_set_mif2_enable(VPP_FLAG_DISABLE);
sclr_set_colorbar(VPP_FLAG_DISABLE,0,0);
//enable
scl_set_int_enable(VPP_FLAG_ENABLE, mod_p->int_catch);
scl_set_watchdog(fb_p->wait_ready);
scl_set_csc_mode(fb_p->csc_mode);
sclr_set_media_format(fb_p->media_fmt);
sclr_set_threshold(0xf);
// filter default value
vppif_reg32_write(SCL_1ST_LAYER_BOUNDARY,48);
vppif_reg32_write(SCL_2ND_LAYER_BOUNDARY,16);
vppif_reg32_write(SCL_FIELD_FILTER_Y_THD,8);
vppif_reg32_write(SCL_FIELD_FILTER_C_THD,8);
vppif_reg32_write(SCL_FIELD_FILTER_CONDITION,0);
vppif_reg32_write(SCL_FRAME_FILTER_RGB,0);
vppif_reg32_write(SCL_FRAME_FILTER_SAMPLER,14);
vppif_reg32_write(SCL_FR_FILTER_SCENE_CHG_THD,32);
//enable
scl_set_reg_update(VPP_FLAG_ENABLE);
scl_set_tg_enable(VPP_FLAG_DISABLE);
}
/*----------------------- Function Body --------------------------------------*/
static void lcd_at070tn83_power_on(void)
{
// DPRINT("lcd_at070tn83_power_on\n");
/* TODO */
#if(WMT_CUR_PID == WMT_PID_8425)
vppif_reg32_write(GPIO_BASE_ADDR+0x24,0x7,0,0x7); // GPIO0 gpio enable
vppif_reg32_write(GPIO_BASE_ADDR+0x54,0x7,0,0x7); // GPIO0 output mode
vppif_reg32_write(GPIO_BASE_ADDR+0x84,0x7,0,0x0); // GPIO0 output mode
vppif_reg32_write(GPIO_BASE_ADDR+0x640,0x707,0,0x707); // GPIO0 pull enable
vppif_reg32_write(GPIO_BASE_ADDR+0x84,0x2,1,0x1); // VGL lo
mdelay(8); // delay 5ms
vppif_reg32_write(GPIO_BASE_ADDR+0x84,0x1,0,0x1); // AVDD hi
mdelay(6); // delay 5ms
vppif_reg32_write(GPIO_BASE_ADDR+0x84,0x4,2,0x1); // VGH hi
mdelay(10); // delay 10ms
#endif
}
void govw_set_width(U32 width, U32 fb_width)
{
vdo_color_fmt colfmt;
DBG_DETAIL("w %d,fbw %d\n",width,fb_width);
colfmt = govw_get_color_format();
vppif_reg32_write(GOVW_HD_YPXLWID, width);
vppif_reg32_write(GOVW_HD_YBUFWID, fb_width);
if( colfmt == VDO_COL_FMT_YUV444 ){
vppif_reg32_write(GOVW_HD_CBUFWID, fb_width * 2);
vppif_reg32_write(GOVW_HD_CPXLWID, width);
}
else {
vppif_reg32_write(GOVW_HD_CBUFWID, fb_width);
vppif_reg32_write(GOVW_HD_CPXLWID, width/2);
}
}
void wmt_cec_do_resume(void)
{
vppif_reg32_out(REG_VPP_SWRST2_SEL, 0x1011111);
/* disable GPIO function */
vppif_reg32_write(GPIO_BASE_ADDR + 0x40, BIT4, 4, 0);
/* GPIO4 disable GPIO out */
vppif_reg32_write(GPIO_BASE_ADDR + 0x80, BIT4, 4, 0);
/* GPIO4 disable pull ctrl */
vppif_reg32_write(GPIO_BASE_ADDR + 0x480, BIT4, 4, 0);
/* Suspend GPIO output enable */
vppif_reg32_write(GPIO_BASE_ADDR + 0x80, BIT23, 23, 1);
/* Suspend GPIO output high */
vppif_reg32_write(GPIO_BASE_ADDR + 0xC0, BIT23, 23, 1);
/* Wake3 disable pull ctrl */
vppif_reg32_write(GPIO_BASE_ADDR + 0x480, BIT19, 19, 0);
vpp_restore_reg(REG_CEC_BEGIN,
(REG_CEC_END - REG_CEC_BEGIN), wmt_cec_pm_bk);
wmt_cec_pm_bk = 0;
}
void scl_set_int_enable(vpp_flag_t enable, vpp_int_t int_bit)
{
//clean status first before enable/disable interrupt
scl_clean_int_status(int_bit);
if (int_bit & VPP_INT_ERR_SCL_TG) {
vppif_reg32_write(SCLW_INT_TGERR_ENABLE, enable);
}
if (int_bit & VPP_INT_ERR_SCLR1_MIF) {
vppif_reg32_write(SCLW_INT_R1MIF_ENABLE, enable);
}
if (int_bit & VPP_INT_ERR_SCLR2_MIF) {
vppif_reg32_write(SCLW_INT_R2MIF_ENABLE, enable);
}
if (int_bit & VPP_INT_ERR_SCLW_MIFRGB) {
vppif_reg32_write(SCLW_INT_WMIFRGB_ENABLE, enable);
}
if (int_bit & VPP_INT_ERR_SCLW_MIFY) {
vppif_reg32_write(SCLW_INT_WMIFYERR_ENABLE, enable);
}
if (int_bit & VPP_INT_ERR_SCLW_MIFC) {
vppif_reg32_write(SCLW_INT_WMIFCERR_ENABLE, enable);
}
}
void govw_set_timing(vpp_clock_t *timing,unsigned int pixel_clock)
{
int tg_bk;
DBG_MSG("govw set timing\n");
timing->read_cycle = ( timing->read_cycle < WMT_GOVW_RCYC_MIN )? WMT_GOVW_RCYC_MIN:timing->read_cycle;
timing->read_cycle = ( timing->read_cycle > 255 )? 0xFF:timing->read_cycle;
tg_bk = vppif_reg32_read(GOVW_TG_ENABLE);
vppif_reg32_write(GOVW_TG_ENABLE,0);
vppif_reg32_write(GOVW_TG_RDCYC,timing->read_cycle);
vppif_reg32_write(GOVW_TG_H_ALLPIXEL,timing->total_pixel_of_line);
vppif_reg32_write(GOVW_TG_H_ACTBG,timing->begin_pixel_of_active);
vppif_reg32_write(GOVW_TG_H_ACTEND,timing->end_pixel_of_active);
vppif_reg32_write(GOVW_TG_V_ALLLINE,timing->total_line_of_frame);
vppif_reg32_write(GOVW_TG_V_ACTBG,timing->begin_line_of_active);
vppif_reg32_write(GOVW_TG_V_ACTEND,timing->end_line_of_active);
vppif_reg32_write(GOVW_TG_VBIE,timing->line_number_between_VBIS_VBIE);
//vppif_reg32_write(GOVW_TG_PVBI,timing->line_number_between_PVBI_VBIS);
vppif_reg32_write(GOVW_TG_PVBI,10);
vppif_reg32_write(GOVW_TG_ENABLE,tg_bk);
DBG_DETAIL("H beg %d,end %d,total %d\n",
timing->begin_pixel_of_active,timing->end_pixel_of_active,timing->total_pixel_of_line);
DBG_DETAIL("V beg %d,end %d,total %d\n",
timing->begin_line_of_active,timing->end_line_of_active,timing->total_line_of_frame);
}
void wmt_cec_init_hw(void)
{
wmt_cec_set_clock();
vppif_reg32_write(CEC_WR_RETRY, 3);
vppif_reg32_out(REG_CEC_RX_TRIG_RANGE, 2);
vppif_reg32_write(CEC_FREE_3X, 3);
vppif_reg32_write(CEC_FREE_5X, 5);
vppif_reg32_write(CEC_FREE_7X, 7);
vppif_reg32_write(CEC_COMP_DISABLE, 1);
vppif_reg32_write(CEC_ERR_HANDLE_DISABLE, 0);
vppif_reg32_write(CEC_NO_ACK_DISABLE, 0);
vppif_reg32_write(CEC_DECODE_FULL_DISABLE, 0);
vppif_reg32_write(CEC_STATUS4_START_DISABLE, 1);
vppif_reg32_write(CEC_STATUS4_LOGIC0_DISABLE, 1);
vppif_reg32_write(CEC_STATUS4_LOGIC1_DISABLE, 1);
/* 1 : read self write and all dest data */
vppif_reg32_write(CEC_RD_ENCODE_ENABLE, 0);
}
void wmt_cec_enable_loopback(int enable)
{
/* 1 : read self write and all dest data */
vppif_reg32_write(CEC_RD_ENCODE_ENABLE, enable);
}
void govm_set_clamping_enable(vpp_flag_t enable)
{
vppif_reg32_write(GOVM_CLAMPING_ENABLE, enable);
}
void lvds_set_rgb_type(int mode)
{
/* 0:888, 1-555, 2-666, 3-565 */
vppif_reg32_write(LVDS_IGS_BPP_TYPE,mode);
}
void govm_set_pip_field(vpp_display_format_t field)
{
vppif_reg32_write(GOVM_PIP_OUTFMT_FIELD,field); /*0:Frame, 1:Field */
}
void govm_set_int_enable(vpp_flag_t enable)
{
vppif_reg32_write(GOVM_INT_ENABLE, enable);
}
void govw_set_reg_update(vpp_flag_t enable)
{
vppif_reg32_write(GOVW_REG_UPDATE, enable);
}
void govm_set_pip_interlace(vpp_flag_t enable)
{
vppif_reg32_write(GOVM_PIP_INTERLACE,enable);
}
void govm_set_dominate(vpp_flag_t pip)
{
/* 0: PIP overlap VPU, 1: VPU overlap PIP */
vppif_reg32_write(GOVM_PIP_DOMINATE,(pip)?0:1);
}
void govm_set_pip_colorbar(vpp_flag_t enable,int width, int inverse)
{
#ifdef GOVM_PIP_COLBAR_ENABLE
vppif_reg32_write(GOVM_PIP_COLBAR_ENABLE,enable);
#endif
}
void govm_set_colorbar(vpp_flag_t enable,int width, int inverse)
{
vppif_reg32_write(GOVM_COLBAR_ENABLE, enable);
vppif_reg32_write(GOVM_COLBAR_MODE, width);
vppif_reg32_write(GOVM_COLBAR_INVERSION, inverse);
}
void wmt_cec_rx_enable(int enable)
{
vppif_reg32_write(CEC_REJECT_NEXT_DECODE, (enable) ? 0 : 1);
/* GPIO4 disable GPIO function */
vppif_reg32_write(GPIO_BASE_ADDR + 0x40, BIT4, 4, (enable) ? 0 : 1);
}
/*----------------------- Function Body --------------------------------------*/
void lvds_set_enable(vpp_flag_t enable)
{
vppif_reg32_write(LVDS_CTL,(enable)? 2:0); // LVDS(0x2) or HDMI(0x0)
// vppif_reg32_write(LVDS_PD,(enable)?0:1);
}
void wmt_cec_enable_int(int no, int enable)
{
vppif_reg32_write(REG_CEC_INT_ENABLE, 0x1 << no, no, enable);
}
void govm_set_pip_fb_width(unsigned int width,unsigned int buf_width)
{
vppif_reg32_write(GOVM_PIP_XWIDTH, width);
vppif_reg32_write(GOVM_PIP_FBUF_WIDTH, buf_width);
}
void govm_set_gamma_mode(int mode)
{
vppif_reg32_write(GOVM_GAMMA_MODE,mode);
}
vpp_flag_t govw_set_hd_color_format(vdo_color_fmt format)
{
switch (format) {
case VDO_COL_FMT_YUV422H:
vppif_reg32_write(GOVW_COLFMT_RGB, 0);
vppif_reg32_write(GOVW_HD_COLFMT, 0);
break;
case VDO_COL_FMT_YUV444:
vppif_reg32_write(GOVW_COLFMT_RGB, 0);
vppif_reg32_write(GOVW_HD_COLFMT, 1);
break;
case VDO_COL_FMT_ARGB:
vppif_reg32_write(GOVW_COLFMT_RGB, 1);
vppif_reg32_write(GOVW_RGB_MODE,0);
break;
case VDO_COL_FMT_RGB_1555:
vppif_reg32_write(GOVW_COLFMT_RGB, 1);
vppif_reg32_write(GOVW_RGB_MODE,1);
break;
case VDO_COL_FMT_RGB_666:
vppif_reg32_write(GOVW_COLFMT_RGB, 1);
vppif_reg32_write(GOVW_RGB_MODE,2);
break;
case VDO_COL_FMT_RGB_565:
vppif_reg32_write(GOVW_COLFMT_RGB, 1);
vppif_reg32_write(GOVW_RGB_MODE,3);
break;
default:
DBGMSG("*E* check the parameter.\n");
return VPP_FLAG_ERROR;
}
return VPP_FLAG_SUCCESS;
}
void govm_set_pip_crop(unsigned int h_crop,unsigned int v_crop)
{
vppif_reg32_write(GOVM_PIP_HCROP, h_crop);
vppif_reg32_write(GOVM_PIP_VCROP, v_crop);
}
