static int siu_startup(struct uart_port *port)
{
int retval;
if (port->membase == NULL)
return -ENODEV;
siu_clear_fifo(port);
(void)siu_read(port, UART_LSR);
(void)siu_read(port, UART_RX);
(void)siu_read(port, UART_IIR);
(void)siu_read(port, UART_MSR);
if (siu_read(port, UART_LSR) == 0xff)
return -ENODEV;
retval = request_irq(port->irq, siu_interrupt, 0, siu_type_name(port), port);
if (retval)
return retval;
if (port->type == PORT_VR41XX_DSIU)
vr41xx_enable_dsiuint(DSIUINT_ALL);
siu_write(port, UART_LCR, UART_LCR_WLEN8);
spin_lock_irq(&port->lock);
siu_set_mctrl(port, port->mctrl);
spin_unlock_irq(&port->lock);
siu_write(port, UART_IER, UART_IER_RLSI | UART_IER_RDI);
(void)siu_read(port, UART_LSR);
(void)siu_read(port, UART_RX);
(void)siu_read(port, UART_IIR);
(void)siu_read(port, UART_MSR);
return 0;
}
static int __init vr41xx_icu_init(void)
{
unsigned long icu1_start, icu2_start;
int i;
switch (current_cpu_data.cputype) {
case CPU_VR4111:
case CPU_VR4121:
icu1_start = ICU1_TYPE1_BASE;
icu2_start = ICU2_TYPE1_BASE;
break;
case CPU_VR4122:
case CPU_VR4131:
case CPU_VR4133:
icu1_start = ICU1_TYPE2_BASE;
icu2_start = ICU2_TYPE2_BASE;
break;
default:
printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n");
return -ENODEV;
}
if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL)
return -EBUSY;
if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) {
release_mem_region(icu1_start, ICU1_SIZE);
return -EBUSY;
}
icu1_base = ioremap(icu1_start, ICU1_SIZE);
if (icu1_base == NULL) {
release_mem_region(icu1_start, ICU1_SIZE);
release_mem_region(icu2_start, ICU2_SIZE);
return -ENOMEM;
}
icu2_base = ioremap(icu2_start, ICU2_SIZE);
if (icu2_base == NULL) {
iounmap(icu1_base);
release_mem_region(icu1_start, ICU1_SIZE);
release_mem_region(icu2_start, ICU2_SIZE);
return -ENOMEM;
}
icu1_write(MSYSINT1REG, 0);
icu1_write(MGIUINTLREG, 0xffff);
icu2_write(MSYSINT2REG, 0);
icu2_write(MGIUINTHREG, 0xffff);
for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
irq_desc[i].handler = &sysint1_irq_type;
for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
irq_desc[i].handler = &sysint2_irq_type;
cascade_irq(INT0_IRQ, icu_get_irq);
cascade_irq(INT1_IRQ, icu_get_irq);
cascade_irq(INT2_IRQ, icu_get_irq);
cascade_irq(INT3_IRQ, icu_get_irq);
cascade_irq(INT4_IRQ, icu_get_irq);
vr41xx_enable_dsiuint(DSIUINT_ALL);
return 0;
}
