static int board_asus_a7v8x_mx(const char *name)
{
struct pci_dev *dev;
uint8_t val;
dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
if (!dev)
dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */
if (!dev) {
fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
return -1;
}
/* This bit is marked reserved actually */
val = pci_read_byte(dev, 0x59);
val &= 0x7F;
pci_write_byte(dev, 0x59, val);
/* Raise ROM MEMW# line on Winbond w83697 SuperIO */
w836xx_ext_enter();
if (!(wbsio_read(0x24) & 0x02)) /* flash rom enabled? */
wbsio_mask(0x24, 0x08, 0x08); /* enable MEMW# */
w836xx_ext_leave();
return 0;
}
static int w83627hf_gpio24_raise(const char *name)
{
w836xx_ext_enter();
/* Is this the w83627hf? */
if (wbsio_read(0x20) != 0x52) { /* SIO device ID register */
fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
name, wbsio_read(0x20));
w836xx_ext_leave();
return -1;
}
/* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
wbsio_mask(0x2B, 0x10, 0x10);
wbsio_write(0x07, 0x08); /* Select logical device 8: GPIO port 2 */
wbsio_mask(0x30, 0x01, 0x01); /* Activate logical device. */
wbsio_mask(0xF0, 0x00, 0x10); /* GPIO24 -> output */
wbsio_mask(0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
wbsio_mask(0xF1, 0x10, 0x10); /* Raise GPIO24 */
w836xx_ext_leave();
return 0;
}
static uint16_t wbsio_get_spibase(uint16_t port)
{
uint8_t id;
uint16_t flashport = 0;
w836xx_ext_enter(port);
id = sio_read(port, 0x20);
if (id != 0xa0) {
msg_perr("\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id);
goto done;
}
if (0 == (sio_read(port, 0x24) & 2)) {
msg_perr("\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port);
goto done;
}
sio_write(port, 0x07, 0x06);
if (0 == (sio_read(port, 0x30) & 1)) {
msg_perr("\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port);
goto done;
}
flashport = (sio_read(port, 0x62) << 8) | sio_read(port, 0x63);
done:
w836xx_ext_leave(port);
return flashport;
}
