/*!
* This function puts the CPU into idle mode. It is called by default_idle()
* in process.c file.
*/
void arch_idle(void)
{
if (likely(!mxc_jtag_enabled)) {
if (ddr_clk == NULL)
ddr_clk = clk_get(NULL, "ddr_clk");
if (gpc_dvfs_clk == NULL)
gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk");
/* gpc clock is needed for SRPG */
clk_enable(gpc_dvfs_clk);
mxc_cpu_lp_set(arch_idle_mode);
if (cpu_is_mx50() && (clk_get_usecount(ddr_clk) == 0)) {
memcpy(wait_in_iram_base, mx50_wait, SZ_4K);
wait_in_iram = (void *)wait_in_iram_base;
if (low_bus_freq_mode) {
u32 reg, cpu_podf;
reg = __raw_readl(apll_base + 0x50);
reg = 0x120490;
__raw_writel(reg, apll_base + 0x50);
reg = __raw_readl(apll_base + 0x80);
reg |= 1;
__raw_writel(reg, apll_base + 0x80);
/* Move ARM to be sourced from 24MHz XTAL.
* when ARM is in WFI.
*/
if (pll1_sw_clk == NULL)
pll1_sw_clk = clk_get(NULL,
"pll1_sw_clk");
if (osc == NULL)
osc = clk_get(NULL, "lp_apm");
if (pll1_main_clk == NULL)
pll1_main_clk = clk_get(NULL,
"pll1_main_clk");
clk_set_parent(pll1_sw_clk, osc);
/* Set the ARM-PODF divider to 1. */
cpu_podf = __raw_readl(MXC_CCM_CACRR);
__raw_writel(0x01, MXC_CCM_CACRR);
wait_in_iram(ccm_base, databahn_base);
/* Set the ARM-POD divider back
* to the original.
*/
__raw_writel(cpu_podf, MXC_CCM_CACRR);
clk_set_parent(pll1_sw_clk, pll1_main_clk);
} else
wait_in_iram(ccm_base, databahn_base);
} else
cpu_do_idle();
clk_disable(gpc_dvfs_clk);
clk_put(ddr_clk);
}
}
/*!
* This function puts the CPU into idle mode. It is called by default_idle()
* in process.c file.
*/
void arch_idle(void)
{
if (likely(!mxc_jtag_enabled)) {
if (ddr_clk == NULL)
ddr_clk = clk_get(NULL, "ddr_clk");
if (gpc_dvfs_clk == NULL)
gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk");
/* gpc clock is needed for SRPG */
clk_enable(gpc_dvfs_clk);
mxc_cpu_lp_set(arch_idle_mode);
if (cpu_is_mx50() && (clk_get_usecount(ddr_clk) == 0)) {
if (sys_clk == NULL)
sys_clk = clk_get(NULL, "sys_clk");
if (low_bus_freq_mode) {
u32 reg, cpu_podf;
reg = __raw_readl(apll_base + 0x50);
reg = 0x120490;
__raw_writel(reg, apll_base + 0x50);
reg = __raw_readl(apll_base + 0x80);
reg |= 1;
__raw_writel(reg, apll_base + 0x80);
if (mx50_ddr_type != MX50_DDR2) {
/* Move ARM to be sourced from 24MHz XTAL.
* when ARM is in WFI.
*/
if (pll1_sw_clk == NULL)
pll1_sw_clk = clk_get(NULL,
"pll1_sw_clk");
if (osc == NULL)
osc = clk_get(NULL, "lp_apm");
if (pll1_main_clk == NULL)
pll1_main_clk = clk_get(NULL,
"pll1_main_clk");
clk_set_parent(pll1_sw_clk, osc);
/* Set the ARM-PODF divider to 1. */
cpu_podf = __raw_readl(MXC_CCM_CACRR);
__raw_writel(0x01, MXC_CCM_CACRR);
while (__raw_readl(MXC_CCM_CDHIPR) &
MXC_CCM_CDHIPR_ARM_PODF_BUSY)
;
}
wait_in_iram(ccm_base, databahn_base,
clk_get_usecount(sys_clk));
if (mx50_ddr_type != MX50_DDR2) {
/* Set the ARM-POD divider back
* to the original.
*/
__raw_writel(cpu_podf, MXC_CCM_CACRR);
while (__raw_readl(MXC_CCM_CDHIPR) &
MXC_CCM_CDHIPR_ARM_PODF_BUSY)
;
clk_set_parent(pll1_sw_clk, pll1_main_clk);
}
} else
wait_in_iram(ccm_base, databahn_base,
clk_get_usecount(sys_clk));
} else if (cpu_is_mx53() && (clk_get_usecount(ddr_clk) == 0)
&& low_bus_freq_mode) {
suspend_in_iram(suspend_param1, NULL, NULL);
} else
cpu_do_idle();
clk_disable(gpc_dvfs_clk);
clk_put(ddr_clk);
}
}
