/*
* Disable the watchdog.
*/
static inline void at32_wdt_stop(void)
{
unsigned long psel;
spin_lock(&wdt->io_lock);
psel = wdt_readl(wdt, CTRL) & WDT_BF(CTRL_PSEL, 0x0f);
wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0x55));
wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0xaa));
spin_unlock(&wdt->io_lock);
}
/*
* Enable and reset the watchdog.
*/
static inline void at32_wdt_start(void)
{
/* 0xf is 2^16 divider = 2 sec, 0xe is 2^15 divider = 1 sec */
unsigned long psel = (wdt->timeout > 1) ? 0xf : 0xe;
spin_lock(&wdt->io_lock);
wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
| WDT_BF(CTRL_PSEL, psel)
| WDT_BF(CTRL_KEY, 0x55));
wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
| WDT_BF(CTRL_PSEL, psel)
| WDT_BF(CTRL_KEY, 0xaa));
spin_unlock(&wdt->io_lock);
}
/* timeout unit us */
static int rk29_wdt_set_heartbeat(int timeout)
{
unsigned int freq = clk_get_rate(wdt_clock);
unsigned int count;
unsigned int torr = 0;
unsigned int acc = 1;
if (timeout < 1)
return -EINVAL;
// freq /= 1000000;
count = timeout * freq;
count /= 0x10000;
while(acc < count){
acc *= 2;
torr++;
}
if(torr > 15){
torr = 15;
}
DBG("%s:%d\n", __func__, torr);
wdt_writel(torr, RK29_WDT_TORR);
return 0;
}
static void rk29_wdt_start(void)
{
unsigned long wtcon;
clk_enable(wdt_clock);
rk29_wdt_set_heartbeat(tmr_margin);
wtcon = (RK29_WDT_EN << 0) | (RK29_RESPONSE_MODE << 1) | (RK29_RESET_PULSE << 2);
wdt_writel(wtcon, RK29_WDT_CR);
}
/*
* Pat the watchdog timer.
*/
static inline void at32_wdt_pat(void)
{
spin_lock(&wdt->io_lock);
wdt_writel(wdt, CLR, 0x42);
spin_unlock(&wdt->io_lock);
}
static void __rk29_wdt_stop(void)
{
rk29_wdt_keepalive(); //feed dog
wdt_writel(0x0a, RK29_WDT_CR);
}
/* functions */
void rk29_wdt_keepalive(void)
{
if (wdt_base)
wdt_writel(0x76, RK29_WDT_CRR);
}
