int board_eth_init(bd_t *bis)
{
int error;
#ifdef CONFIG_FSL_MC_ENET
struct memac_mdio_info *memac_mdio0_info;
struct memac_mdio_info *memac_mdio1_info;
unsigned int i;
initialize_dpmac_to_slot();
memac_mdio0_info = (struct memac_mdio_info *)malloc(
sizeof(struct memac_mdio_info));
memac_mdio0_info->regs =
(struct memac_mdio_controller *)
CONFIG_SYS_FSL_WRIOP1_MDIO1;
memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the real MDIO1 bus */
fm_memac_mdio_init(bis, memac_mdio0_info);
memac_mdio1_info = (struct memac_mdio_info *)malloc(
sizeof(struct memac_mdio_info));
memac_mdio1_info->regs =
(struct memac_mdio_controller *)
CONFIG_SYS_FSL_WRIOP1_MDIO2;
memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the real MDIO2 bus */
fm_memac_mdio_init(bis, memac_mdio1_info);
/* Register the muxing front-ends to the MDIO buses */
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
break;
case PHY_INTERFACE_MODE_SGMII:
ls2085a_handle_phy_interface_sgmii(i);
break;
case PHY_INTERFACE_MODE_XGMII:
ls2085a_handle_phy_interface_xsgmii(i);
break;
default:
break;
}
}
error = cpu_eth_init(bis);
#endif
error = pci_eth_init(bis);
return error;
}
void load_phy_firmware(void)
{
int i;
u8 phy_addr;
struct phy_device *phy_dev;
struct mii_dev *dev;
phy_interface_t interface;
/*Initialize and upload firmware for all the PHYs*/
for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
interface = wriop_get_enet_if(i);
if (interface == PHY_INTERFACE_MODE_XGMII) {
dev = wriop_get_mdio(i);
phy_addr = wriop_get_phy_address(i);
phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
interface);
if (!phy_dev) {
printf("No phydev for phyaddr %d\n", phy_addr);
continue;
}
/*Flash firmware for All CS4340 PHYS */
if (phy_dev->phy_id == PHY_UID_CS4340)
load_firmware_cortina(phy_dev);
}
}
}
int fsl_mc_ldpaa_init(bd_t *bis)
{
int i;
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++)
if (wriop_is_enabled_dpmac(i) == 1)
ldpaa_eth_init(i, wriop_get_enet_if(i));
return 0;
}
static int init_phy(struct eth_device *dev)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
struct phy_device *phydev = NULL;
struct mii_dev *bus;
bus = wriop_get_mdio(priv->dpmac_id);
if (bus == NULL)
return 0;
phydev = phy_connect(bus, wriop_get_phy_address(priv->dpmac_id),
dev, wriop_get_enet_if(priv->dpmac_id));
if (!phydev) {
printf("Failed to connect\n");
return -1;
}
priv->phydev = phydev;
return phy_config(phydev);
}
static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
{
int i, err = 0, ret = 0;
char ethname[ETH_NAME_LEN];
struct eth_device *eth_dev;
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
/* port not enabled */
if (wriop_is_enabled_dpmac(i) != 1)
continue;
snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s", i,
phy_interface_strings[wriop_get_enet_if(i)]);
eth_dev = eth_get_dev_by_name(ethname);
if (eth_dev == NULL)
continue;
switch (type) {
case MC_FIXUP_DPL:
err = mc_fixup_dpl_mac_addr(blob, i, eth_dev);
break;
case MC_FIXUP_DPC:
err = mc_fixup_dpc_mac_addr(blob, i, eth_dev);
break;
default:
break;
}
if (err)
printf("fsl-mc: ERROR fixing mac address for %s\n",
ethname);
ret |= err;
}
return ret;
}
int board_eth_init(bd_t *bis)
{
int error;
#ifdef CONFIG_FSL_MC_ENET
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
struct memac_mdio_info *memac_mdio0_info;
struct memac_mdio_info *memac_mdio1_info;
unsigned int i;
char *env_hwconfig;
env_hwconfig = getenv("hwconfig");
initialize_dpmac_to_slot();
memac_mdio0_info = (struct memac_mdio_info *)malloc(
sizeof(struct memac_mdio_info));
memac_mdio0_info->regs =
(struct memac_mdio_controller *)
CONFIG_SYS_FSL_WRIOP1_MDIO1;
memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the real MDIO1 bus */
fm_memac_mdio_init(bis, memac_mdio0_info);
memac_mdio1_info = (struct memac_mdio_info *)malloc(
sizeof(struct memac_mdio_info));
memac_mdio1_info->regs =
(struct memac_mdio_controller *)
CONFIG_SYS_FSL_WRIOP1_MDIO2;
memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the real MDIO2 bus */
fm_memac_mdio_init(bis, memac_mdio1_info);
/* Register the muxing front-ends to the MDIO buses */
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
ls2080a_handle_phy_interface_qsgmii(i);
break;
case PHY_INTERFACE_MODE_SGMII:
ls2080a_handle_phy_interface_sgmii(i);
break;
case PHY_INTERFACE_MODE_XGMII:
ls2080a_handle_phy_interface_xsgmii(i);
break;
default:
break;
if (i == 16)
i = NUM_WRIOP_PORTS;
}
}
error = cpu_eth_init(bis);
if (hwconfig_f("xqsgmii", env_hwconfig)) {
if (serdes1_prtcl == 0x7)
sgmii_configure_repeater(1);
if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
serdes2_prtcl == 0x49)
sgmii_configure_repeater(2);
}
#endif
error = pci_eth_init(bis);
return error;
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
struct memac_mdio_controller *reg;
srds_s1 = in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the EMI 2 */
fm_memac_mdio_init(bis, &mdio_info);
switch (srds_s1) {
case 0x2A:
wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
break;
default:
printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
srds_s1);
break;
}
for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
interface = wriop_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
wriop_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
wriop_set_mdio(i, dev);
break;
default:
break;
}
}
/* Load CORTINA CS4340 PHY firmware */
load_phy_firmware();
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
#ifdef CONFIG_PHY_AQUANTIA
/*
* Export functions to be used by AQ firmware
* upload application
*/
gd->jt->strcpy = strcpy;
gd->jt->mdelay = mdelay;
gd->jt->mdio_get_current_dev = mdio_get_current_dev;
gd->jt->phy_find_by_mask = phy_find_by_mask;
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
#endif
return pci_eth_init(bis);
}
static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
struct dpni_queue_attr rx_queue_attr;
struct dpmac_link_state dpmac_link_state = { 0 };
#ifdef DEBUG
struct dpni_link_state link_state;
#endif
int err = 0;
struct mii_dev *bus;
phy_interface_t enet_if;
if (net_dev->state == ETH_STATE_ACTIVE)
return 0;
if (get_mc_boot_status() != 0) {
printf("ERROR (MC is not booted)\n");
return -ENODEV;
}
if (get_dpl_apply_status() == 0) {
printf("ERROR (DPL is deployed. No device available)\n");
return -ENODEV;
}
/* DPMAC initialization */
err = ldpaa_dpmac_setup(priv);
if (err < 0)
goto err_dpmac_setup;
#ifdef CONFIG_PHYLIB
if (priv->phydev)
err = phy_startup(priv->phydev);
if (err) {
printf("%s: Could not initialize\n",
priv->phydev->dev->name);
goto err_dpamc_bind;
}
#else
priv->phydev = (struct phy_device *)malloc(sizeof(struct phy_device));
memset(priv->phydev, 0, sizeof(struct phy_device));
priv->phydev->speed = SPEED_1000;
priv->phydev->link = 1;
priv->phydev->duplex = DUPLEX_FULL;
#endif
bus = wriop_get_mdio(priv->dpmac_id);
enet_if = wriop_get_enet_if(priv->dpmac_id);
if ((bus == NULL) &&
(enet_if == PHY_INTERFACE_MODE_XGMII)) {
priv->phydev = (struct phy_device *)
malloc(sizeof(struct phy_device));
memset(priv->phydev, 0, sizeof(struct phy_device));
priv->phydev->speed = SPEED_10000;
priv->phydev->link = 1;
priv->phydev->duplex = DUPLEX_FULL;
}
if (!priv->phydev->link) {
printf("%s: No link.\n", priv->phydev->dev->name);
err = -1;
goto err_dpamc_bind;
}
/* DPMAC binding DPNI */
err = ldpaa_dpmac_bind(priv);
if (err)
goto err_dpamc_bind;
/* DPNI initialization */
err = ldpaa_dpni_setup(priv);
if (err < 0)
goto err_dpni_setup;
err = ldpaa_dpbp_setup();
if (err < 0)
goto err_dpbp_setup;
/* DPNI binding DPBP */
err = ldpaa_dpni_bind(priv);
if (err)
goto err_dpni_bind;
err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dpni->dpni_handle, net_dev->enetaddr);
if (err) {
printf("dpni_add_mac_addr() failed\n");
return err;
}
err = dpni_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
if (err < 0) {
printf("dpni_enable() failed\n");
return err;
}
dpmac_link_state.rate = priv->phydev->speed;
if (priv->phydev->autoneg == AUTONEG_DISABLE)
dpmac_link_state.options &= ~DPMAC_LINK_OPT_AUTONEG;
else
dpmac_link_state.options |= DPMAC_LINK_OPT_AUTONEG;
if (priv->phydev->duplex == DUPLEX_HALF)
dpmac_link_state.options |= DPMAC_LINK_OPT_HALF_DUPLEX;
dpmac_link_state.up = priv->phydev->link;
err = dpmac_set_link_state(dflt_mc_io, MC_CMD_NO_FLAGS,
priv->dpmac_handle, &dpmac_link_state);
if (err < 0) {
printf("dpmac_set_link_state() failed\n");
return err;
}
#ifdef DEBUG
err = dpni_get_link_state(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dpni->dpni_handle, &link_state);
if (err < 0) {
printf("dpni_get_link_state() failed\n");
return err;
}
printf("link status: %d - ", link_state.up);
link_state.up == 0 ? printf("down\n") :
link_state.up == 1 ? printf("up\n") : printf("error state\n");
#endif
/* TODO: support multiple Rx flows */
err = dpni_get_rx_flow(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dpni->dpni_handle, 0, 0, &rx_queue_attr);
if (err) {
printf("dpni_get_rx_flow() failed\n");
goto err_rx_flow;
}
priv->rx_dflt_fqid = rx_queue_attr.fqid;
err = dpni_get_qdid(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle,
&priv->tx_qdid);
if (err) {
printf("dpni_get_qdid() failed\n");
goto err_qdid;
}
return priv->phydev->link;
err_qdid:
err_rx_flow:
dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
err_dpni_bind:
ldpaa_dpbp_free();
err_dpbp_setup:
dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
err_dpni_setup:
err_dpamc_bind:
dpmac_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle);
err_dpmac_setup:
return err;
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct memac_mdio_controller *reg;
u32 srds_s1, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the EMI 2 */
fm_memac_mdio_init(bis, &mdio_info);
switch (srds_s1) {
case 0x1D:
/*
* XFI does not need a PHY to work, but to avoid U-boot use
* default PHY address which is zero to a MAC when it found
* a MAC has no PHY address, we give a PHY address to XFI
* MAC error.
*/
wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a);
wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR);
break;
default:
printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n",
srds_s1);
break;
}
for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) {
interface = wriop_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_QSGMII:
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
wriop_set_mdio(i, dev);
break;
default:
break;
}
}
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
wriop_set_mdio(WRIOP1_DPMAC2, dev);
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
