/*
* Set the DDR BATs to reflect the actual size of DDR.
*
* dram_size is the actual size of DDR, in bytes
*
* Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
* are using a single BAT to cover DDR.
*
* If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
* is not defined) then we might have a situation where U-Boot will attempt
* to relocated itself outside of the region mapped by DBAT0.
* This will cause a machine check.
*
* Currently we are limited to power of two sized DDR since we only use a
* single bat. If a non-power of two size is used that is less than
* CONFIG_MAX_MEM_MAPPED u-boot will crash.
*
*/
void setup_ddr_bat(phys_addr_t dram_size)
{
unsigned long batu, bl;
bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
if (BATU_SIZE(bl) != dram_size) {
u64 sz = (u64)dram_size - BATU_SIZE(bl);
print_size(sz, " left unmapped\n");
}
batu = bl | BATU_VS | BATU_VP;
write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
}
/* Set up BAT registers */
void setup_bats(void)
{
write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L);
write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L);
write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L);
write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L);
write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L);
write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L);
write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L);
write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L);
write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L);
return;
}
void setupBat (ulong size)
{
ulong batu, batl;
int blocksize = 0;
/* Flash 0 */
#if defined (CONFIG_SYS_AMD_BOOT)
batu = CONFIG_SYS_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
#else
batu = CONFIG_SYS_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
#endif
batl = CONFIG_SYS_FLASH0_BASE | 0x22;
write_bat (IBAT0, batu, batl);
write_bat (DBAT0, batu, batl);
/* Flash 1 */
#if defined (CONFIG_SYS_AMD_BOOT)
batu = CONFIG_SYS_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
#else
batu = CONFIG_SYS_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
#endif
batl = CONFIG_SYS_FLASH1_BASE | 0x22;
write_bat (IBAT1, batu, batl);
write_bat (DBAT1, batu, batl);
/* CPLD */
batu = CONFIG_SYS_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
batl = CONFIG_SYS_CPLD_BASE | 0x22;
write_bat (IBAT2, 0, 0);
write_bat (DBAT2, batu, batl);
/* FPGA */
batu = CONFIG_SYS_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
batl = CONFIG_SYS_FPGA_BASE | 0x22;
write_bat (IBAT3, 0, 0);
write_bat (DBAT3, batu, batl);
/* MBAR - Data only */
batu = CONFIG_SYS_MBAR | BPP_RW | BPP_RX;
batl = CONFIG_SYS_MBAR | 0x22;
mtspr (IBAT4L, 0);
mtspr (IBAT4U, 0);
mtspr (DBAT4L, batl);
mtspr (DBAT4U, batu);
/* MBAR - SRAM */
batu = CONFIG_SYS_SRAM_BASE | BPP_RW | BPP_RX;
batl = CONFIG_SYS_SRAM_BASE | 0x42;
mtspr (IBAT5L, batl);
mtspr (IBAT5U, batu);
mtspr (DBAT5L, batl);
mtspr (DBAT5U, batu);
if (size <= 0x800000) /* 8MB */
blocksize = BL_8M << 2;
else if (size <= 0x1000000) /* 16MB */
blocksize = BL_16M << 2;
else if (size <= 0x2000000) /* 32MB */
blocksize = BL_32M << 2;
else if (size <= 0x4000000) /* 64MB */
blocksize = BL_64M << 2;
else if (size <= 0x8000000) /* 128MB */
blocksize = BL_128M << 2;
else if (size <= 0x10000000) /* 256MB */
blocksize = BL_256M << 2;
/* Memory */
batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
batl = CONFIG_SYS_SDRAM_BASE | 0x42;
mtspr (IBAT6L, batl);
mtspr (IBAT6U, batu);
mtspr (DBAT6L, batl);
mtspr (DBAT6U, batu);
/* memory size is less than 256MB */
if (size <= 0x10000000) {
/* Nothing */
batu = 0;
batl = 0;
} else {
size -= 0x10000000;
if (size <= 0x800000) /* 8MB */
blocksize = BL_8M << 2;
else if (size <= 0x1000000) /* 16MB */
blocksize = BL_16M << 2;
else if (size <= 0x2000000) /* 32MB */
blocksize = BL_32M << 2;
else if (size <= 0x4000000) /* 64MB */
blocksize = BL_64M << 2;
else if (size <= 0x8000000) /* 128MB */
blocksize = BL_128M << 2;
else if (size <= 0x10000000) /* 256MB */
blocksize = BL_256M << 2;
batu = (CONFIG_SYS_SDRAM_BASE +
0x10000000) | blocksize | BPP_RW | BPP_RX;
batl = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | 0x42;
}
mtspr (IBAT7L, batl);
mtspr (IBAT7U, batu);
mtspr (DBAT7L, batl);
mtspr (DBAT7U, batu);
}
