/*
* Install the watch registers for the current thread. A maximum of
* four registers are installed although the machine may have more.
*/
void mips_install_watch_registers(void)
{
struct mips3264_watch_reg_state *watches =
¤t->thread.watch.mips3264;
if(watches->trace_type == 0)
{
switch (current_cpu_data.watch_reg_use_cnt) {
default:
BUG();
case 4:
write_c0_watchlo3(watches->watchlo[3]);
/* Write 1 to the I, R, and W bits to clear them, and
1 to G so all ASIDs are trapped. */
write_c0_watchhi3(0x40000007 | watches->watchhi[3]);
case 3:
write_c0_watchlo2(watches->watchlo[2]);
write_c0_watchhi2(0x40000007 | watches->watchhi[2]);
case 2:
write_c0_watchlo1(watches->watchlo[1]);
write_c0_watchhi1(0x40000007 | watches->watchhi[1]);
case 1:
write_c0_watchlo0(watches->watchlo[0]);
write_c0_watchhi0(0x40000007 | watches->watchhi[0]);
}
}else{
switch (current_cpu_data.watch_reg_use_cnt) {
default:
BUG();
case 4:
write_c0_watchlo3(watches->lo[3][smp_processor_id()]);
/* Write 1 to the I, R, and W bits to clear them, and
1 to G so all ASIDs are trapped. */
write_c0_watchhi3(watches->hi[3][smp_processor_id()]);
case 3:
write_c0_watchlo3(watches->lo[2][smp_processor_id()]);
write_c0_watchhi3(watches->hi[2][smp_processor_id()]);
case 2:
write_c0_watchlo3(watches->lo[1][smp_processor_id()]);
write_c0_watchhi3(watches->hi[1][smp_processor_id()]);
case 1:
write_c0_watchlo3(watches->lo[0][smp_processor_id()]);
write_c0_watchhi3(watches->hi[0][smp_processor_id()]);
}
}
}
/*
* Install the watch registers for the current thread. A maximum of
* four registers are installed although the machine may have more.
*/
void rlx_install_watch_registers(void)
{
struct rlx3264_watch_reg_state *watches =
¤t->thread.watch.rlx3264;
unsigned int ctrl;
switch (current_cpu_data.watch_reg_use_cnt) {
default:
BUG();
case 4:
write_c0_watchlo3(watches->watchlo[3]);
write_c0_watchhi3(0x40000000 | watches->watchhi[3]);
write_lxc0_wmpxmask3(watches->wmpxmask[3]);
set_lxc0_wmpctl(WMPCTLF_EE3);
case 3:
write_c0_watchlo2(watches->watchlo[2]);
write_c0_watchhi2(0x40000000 | watches->watchhi[2]);
write_lxc0_wmpxmask2(watches->wmpxmask[2]);
set_lxc0_wmpctl(WMPCTLF_EE2);
case 2:
write_c0_watchlo1(watches->watchlo[1]);
write_c0_watchhi1(0x40000000 | watches->watchhi[1]);
write_lxc0_wmpxmask1(watches->wmpxmask[1]);
set_lxc0_wmpctl(WMPCTLF_EE1);
case 1:
write_c0_watchlo0(watches->watchlo[0]);
write_c0_watchhi0(0x40000000 | watches->watchhi[0]);
write_lxc0_wmpxmask0(watches->wmpxmask[0]);
set_lxc0_wmpctl(WMPCTLF_EE0);
}
/*
* set WMPCTL register
*/
ctrl = read_lxc0_wmpctl();
if (current_cpu_data.watch_mode)
ctrl &= WMPCTLF_MS;
if (current_cpu_data.watch_kernel)
ctrl &= WMPCTLF_KE;
write_lxc0_wmpctl(ctrl);
}
void mips_install_watch_registers(void)
{
struct mips3264_watch_reg_state *watches =
¤t->thread.watch.mips3264;
switch (current_cpu_data.watch_reg_use_cnt) {
default:
BUG();
case 4:
write_c0_watchlo3(watches->watchlo[3]);
write_c0_watchhi3(0x40000007 | watches->watchhi[3]);
case 3:
write_c0_watchlo2(watches->watchlo[2]);
write_c0_watchhi2(0x40000007 | watches->watchhi[2]);
case 2:
write_c0_watchlo1(watches->watchlo[1]);
write_c0_watchhi1(0x40000007 | watches->watchhi[1]);
case 1:
write_c0_watchlo0(watches->watchlo[0]);
write_c0_watchhi0(0x40000007 | watches->watchhi[0]);
}
}
__cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
{
unsigned int t;
if ((c->options & MIPS_CPU_WATCH) == 0)
return;
/*
* Check which of the I,R and W bits are supported, then
* disable the register.
*/
write_c0_watchlo0(7);
t = read_c0_watchlo0();
write_c0_watchlo0(0);
c->watch_reg_masks[0] = t & 7;
/* Write the mask bits and read them back to determine which
* can be used. */
c->watch_reg_count = 1;
c->watch_reg_use_cnt = 1;
t = read_c0_watchhi0();
write_c0_watchhi0(t | 0xff8);
t = read_c0_watchhi0();
c->watch_reg_masks[0] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo1(7);
t = read_c0_watchlo1();
write_c0_watchlo1(0);
c->watch_reg_masks[1] = t & 7;
c->watch_reg_count = 2;
c->watch_reg_use_cnt = 2;
t = read_c0_watchhi1();
write_c0_watchhi1(t | 0xff8);
t = read_c0_watchhi1();
c->watch_reg_masks[1] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo2(7);
t = read_c0_watchlo2();
write_c0_watchlo2(0);
c->watch_reg_masks[2] = t & 7;
c->watch_reg_count = 3;
c->watch_reg_use_cnt = 3;
t = read_c0_watchhi2();
write_c0_watchhi2(t | 0xff8);
t = read_c0_watchhi2();
c->watch_reg_masks[2] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo3(7);
t = read_c0_watchlo3();
write_c0_watchlo3(0);
c->watch_reg_masks[3] = t & 7;
c->watch_reg_count = 4;
c->watch_reg_use_cnt = 4;
t = read_c0_watchhi3();
write_c0_watchhi3(t | 0xff8);
t = read_c0_watchhi3();
c->watch_reg_masks[3] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
/* We use at most 4, but probe and report up to 8. */
c->watch_reg_count = 5;
t = read_c0_watchhi4();
if ((t & 0x80000000) == 0)
return;
c->watch_reg_count = 6;
t = read_c0_watchhi5();
if ((t & 0x80000000) == 0)
return;
c->watch_reg_count = 7;
t = read_c0_watchhi6();
if ((t & 0x80000000) == 0)
return;
c->watch_reg_count = 8;
}
void __cpuinit rlx_probe_watch_registers(struct cpuinfo_mips *c)
{
unsigned int t;
if ((c->options & MIPS_CPU_WATCH) == 0)
return;
/*
* Check which of the I,R and W bits are supported, then
* disable the register.
*/
write_c0_watchlo0(7);
t = read_c0_watchlo0();
write_c0_watchlo0(0);
c->watch_reg_masks[0] = t & 7;
/* Write the mask bits and read them back to determine which
* can be used. */
c->watch_reg_count = 1;
c->watch_reg_use_cnt = 1;
t = read_c0_watchhi0();
write_c0_watchhi0(t | 0xff8);
t = read_c0_watchhi0();
c->watch_reg_masks[0] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo1(7);
t = read_c0_watchlo1();
write_c0_watchlo1(0);
c->watch_reg_masks[1] = t & 7;
c->watch_reg_count = 2;
c->watch_reg_use_cnt = 2;
t = read_c0_watchhi1();
write_c0_watchhi1(t | 0xff8);
t = read_c0_watchhi1();
c->watch_reg_masks[1] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo2(7);
t = read_c0_watchlo2();
write_c0_watchlo2(0);
c->watch_reg_masks[2] = t & 7;
c->watch_reg_count = 3;
c->watch_reg_use_cnt = 3;
t = read_c0_watchhi2();
write_c0_watchhi2(t | 0xff8);
t = read_c0_watchhi2();
c->watch_reg_masks[2] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo3(7);
t = read_c0_watchlo3();
write_c0_watchlo3(0);
c->watch_reg_masks[3] = t & 7;
c->watch_reg_count = 4;
c->watch_reg_use_cnt = 4;
t = read_c0_watchhi3();
write_c0_watchhi3(t | 0xff8);
t = read_c0_watchhi3();
c->watch_reg_masks[3] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
/* taroko processor can be configured for more than 4
* registers */
write_c0_watchlo4(7);
t = read_c0_watchlo4();
write_c0_watchlo4(0);
c->watch_reg_count = 5;
c->watch_reg_use_cnt = 5;
t = read_c0_watchhi4();
write_c0_watchhi4(t | 0xff8);
t = read_c0_watchhi4();
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo5(7);
t = read_c0_watchlo5();
write_c0_watchlo5(0);
c->watch_reg_count = 6;
c->watch_reg_use_cnt = 6;
t = read_c0_watchhi5();
write_c0_watchhi5(t | 0xff8);
t = read_c0_watchhi5();
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo6(7);
t = read_c0_watchlo6();
write_c0_watchlo6(0);
c->watch_reg_count = 7;
c->watch_reg_use_cnt = 7;
t = read_c0_watchhi6();
write_c0_watchhi6(t | 0xff8);
t = read_c0_watchhi6();
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo7(7);
t = read_c0_watchlo7();
write_c0_watchlo7(0);
c->watch_reg_count = 8;
c->watch_reg_use_cnt = 8;
t = read_c0_watchhi7();
write_c0_watchhi7(t | 0xff8);
t = read_c0_watchhi7();
if ((t & 0x80000000) == 0)
return;
}
__cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
{
unsigned int t;
if ((c->options & MIPS_CPU_WATCH) == 0)
return;
write_c0_watchlo0(7);
t = read_c0_watchlo0();
write_c0_watchlo0(0);
c->watch_reg_masks[0] = t & 7;
c->watch_reg_count = 1;
c->watch_reg_use_cnt = 1;
t = read_c0_watchhi0();
write_c0_watchhi0(t | 0xff8);
t = read_c0_watchhi0();
c->watch_reg_masks[0] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo1(7);
t = read_c0_watchlo1();
write_c0_watchlo1(0);
c->watch_reg_masks[1] = t & 7;
c->watch_reg_count = 2;
c->watch_reg_use_cnt = 2;
t = read_c0_watchhi1();
write_c0_watchhi1(t | 0xff8);
t = read_c0_watchhi1();
c->watch_reg_masks[1] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo2(7);
t = read_c0_watchlo2();
write_c0_watchlo2(0);
c->watch_reg_masks[2] = t & 7;
c->watch_reg_count = 3;
c->watch_reg_use_cnt = 3;
t = read_c0_watchhi2();
write_c0_watchhi2(t | 0xff8);
t = read_c0_watchhi2();
c->watch_reg_masks[2] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo3(7);
t = read_c0_watchlo3();
write_c0_watchlo3(0);
c->watch_reg_masks[3] = t & 7;
c->watch_reg_count = 4;
c->watch_reg_use_cnt = 4;
t = read_c0_watchhi3();
write_c0_watchhi3(t | 0xff8);
t = read_c0_watchhi3();
c->watch_reg_masks[3] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
c->watch_reg_count = 5;
t = read_c0_watchhi4();
if ((t & 0x80000000) == 0)
return;
c->watch_reg_count = 6;
t = read_c0_watchhi5();
if ((t & 0x80000000) == 0)
return;
c->watch_reg_count = 7;
t = read_c0_watchhi6();
if ((t & 0x80000000) == 0)
return;
c->watch_reg_count = 8;
}
