uptime_Hz = ulBSP430uptimeConversionFrequency_Hz_ni();
hh10d.sample_duration_utt = uptime_Hz;
cprintf("HH10D I2C on %s at %p, bus rate %lu Hz, address 0x%02x\n",
xBSP430serialName(APP_HH10D_I2C_PERIPH_HANDLE) ?: "UNKNOWN",
i2c, ulBSP430clockSMCLK_Hz_ni() / APP_HH10D_I2C_PRESCALER,
APP_HH10D_I2C_ADDRESS);
#if BSP430_PLATFORM_PERIPHERAL_HELP
cprintf("HH10D I2C Pins: %s\n", xBSP430platformPeripheralHelp(APP_HH10D_I2C_PERIPH_HANDLE, BSP430_PERIPHCFG_SERIAL_I2C));
#endif /* BSP430_PLATFORM_PERIPHERAL_HELP */
cprintf("Monitoring HH10D on %s.%u using timer %s\n",
xBSP430portName(APP_HH10D_PORT_PERIPH_HANDLE) ?: "P?",
bitToPin(APP_HH10D_PORT_BIT),
xBSP430timerName(APP_HH10D_TIMER_PERIPH_HANDLE) ?: "T?");
cprintf("Uptime CC block %s.%u at %u Hz sample duration %u ticks\n",
xBSP430timerName(BSP430_UPTIME_TIMER_PERIPH_HANDLE),
APP_HH10D_UPTIME_CC_INDEX, uptime_Hz, hh10d.sample_duration_utt);
i2c = hBSP430serialOpenI2C(i2c,
BSP430_SERIAL_ADJUST_CTL0_INITIALIZER(UCMST),
UCSSEL_2, APP_HH10D_I2C_PRESCALER);
if (! i2c) {
cprintf("I2C open failed.\n");
return;
}
(void)iBSP430i2cSetAddresses_ni(i2c, -1, APP_HH10D_I2C_ADDRESS);
hh10d_sens = 0;
{
int rc;
void main ()
{
hBSP430timerMuxSharedAlarm map;
tBSP430periphHandle uptime_periph;
int arc[sizeof(mux_alarms)/sizeof(*mux_alarms)];
unsigned long last_wake_utt;
unsigned long last_sleep_utt;
int rc = 0;
vBSP430platformInitialize_ni();
last_wake_utt = ulBSP430uptime_ni();
(void)iBSP430consoleInitialize();
BSP430_CORE_ENABLE_INTERRUPT();
cprintf("\n\nevent demo " __DATE__ " " __TIME__ "\n");
mux_tag = ucBSP430eventTagAllocate("MuxAlarm");
stats_tag = ucBSP430eventTagAllocate("Statistics");
mux_flag = uiBSP430eventFlagAllocate();
uptime_periph = xBSP430periphFromHPL(hBSP430uptimeTimer()->hpl);
map = hBSP430timerMuxAlarmStartup(&mux_alarm_base, uptime_periph, UPTIME_MUXALARM_CCIDX);
cprintf("Mux tag %u, stats tag %u, flag %x, with alarm base %p on %s.%u\n",
mux_tag, stats_tag, mux_flag, map,
xBSP430timerName(uptime_periph), UPTIME_MUXALARM_CCIDX);
if (! map) {
cprintf("ERR initializing mux shared alarm\n");
goto err_out;
}
/* Processing done entirely in mux callback. No wakeup. */
mux_alarms[0].alarm.callback_ni = mux_alarm_callback;
mux_alarms[0].interval_utt = BSP430_UPTIME_MS_TO_UTT(150);
/* Processing done by an event flag */
mux_alarms[1].alarm.callback_ni = mux_alarm_callback;
mux_alarms[1].interval_utt = BSP430_UPTIME_MS_TO_UTT(500);
mux_alarms[1].flag = mux_flag;
/* Processing done by a callback with a timestamped event */
mux_alarms[2].alarm.callback_ni = mux_alarm_callback;
mux_alarms[2].interval_utt = BSP430_UPTIME_MS_TO_UTT(700);
mux_alarms[2].process_fn = process_timestamp;
mux_alarms[2].tag = mux_tag;
/* Processing done by a callback with a timestamped event */
mux_alarms[3].alarm.callback_ni = mux_alarm_callback;
mux_alarms[3].interval_utt = BSP430_UPTIME_MS_TO_UTT(10000);
mux_alarms[3].process_fn = process_statistics;
mux_alarms[3].tag = stats_tag;
/* Enable the multiplexed alarms */
BSP430_CORE_DISABLE_INTERRUPT();
do {
int i = 0;
for (i = 0; (0 == rc) && (i < sizeof(mux_alarms)/sizeof(*mux_alarms)); ++i) {
mux_alarms[i].alarm.setting_tck = ulBSP430uptime_ni();
arc[i] = iBSP430timerMuxAlarmAdd_ni(map, &mux_alarms[i].alarm);
}
} while (0);
BSP430_CORE_ENABLE_INTERRUPT();
/* Display the results. All values should be non-negative for success. */
{
int i;
cprintf("Alarm installation got:");
rc = 0;
for (i = 0; i < sizeof(arc)/sizeof(*arc); ++i) {
cprintf(" %d", arc[i]);
if (0 > arc[i]) {
rc = arc[i];
}
}
cputchar('\n');
}
if (0 > rc) {
goto err_out;
}
last_sleep_utt = ulBSP430uptime();
while (1) {
last_wake_utt = ulBSP430uptime();
unsigned int events = process_events(uiBSP430eventFlagsGet());
if (events) {
cprintf("ERR: Unprocessed event flags %04x\n", events);
}
BSP430_CORE_DISABLE_INTERRUPT();
/* Put back any unprocessed events */
vBSP430eventFlagsSet_ni(events);
if (iBSP430eventFlagsEmpty_ni()) {
/* Nothing pending: go to sleep, then jump back to the loop head
* when we get woken. */
statistics_v.sleep_utt += last_wake_utt - last_sleep_utt;
last_sleep_utt = ulBSP430uptime_ni();
statistics_v.awake_utt += last_sleep_utt - last_wake_utt;
statistics_v.sleep_ct += 1;
BSP430_CORE_LPM_ENTER_NI(LPM4_bits | GIE);
continue;
}
BSP430_CORE_ENABLE_INTERRUPT();
}
err_out:
(void)iBSP430consoleFlush();
return;
}
void main ()
{
volatile sBSP430hplTIMER * const timer_hpl = xBSP430hplLookupTIMER(BSP430_TIMER_CCACLK_PERIPH_HANDLE);
unsigned int outclk;
unsigned int last_outclk;
unsigned int cctl;
hBSP430halPORT const inclk_port_hal = hBSP430portLookup(BSP430_TIMER_CCACLK_CLK_PORT_PERIPH_HANDLE);
hBSP430halPORT const cc_port_hal = hBSP430portLookup(APP_CC_PORT_PERIPH_HANDLE);
hBSP430halPORT const outclk_port_hal = hBSP430portLookup(APP_OUTCLK_PORT_PERIPH_HANDLE);
hBSP430halPORT const trigger_port_hal = hBSP430portLookup(APP_TRIGGER_PORT_PERIPH_HANDLE);
vBSP430platformInitialize_ni();
vBSP430unittestInitialize();
cprintf("timer_scs_test: " __DATE__ " " __TIME__ "\n");
if (NULL == timer_hpl) {
cprintf("ERROR: Unable to get timer HPL access\n");
return;
}
if (NULL == inclk_port_hal) {
cprintf("ERROR: Unable to get INCLK port access\n");
return;
}
if (NULL == cc_port_hal) {
cprintf("ERROR: Unable to get CC0 port access\n");
return;
}
if (NULL == outclk_port_hal) {
cprintf("ERROR: Unable to get OUTCLK port access\n");
return;
}
if (NULL == trigger_port_hal) {
cprintf("ERROR: Unable to get TRIGGER port access\n");
return;
}
cprintf("Please connect OUTCLK at %s.%u to %s INCLK at %s.%u\n",
xBSP430portName(APP_OUTCLK_PORT_PERIPH_HANDLE),
iBSP430portBitPosition(APP_OUTCLK_PORT_BIT),
xBSP430timerName(BSP430_TIMER_CCACLK_PERIPH_HANDLE),
xBSP430portName(BSP430_TIMER_CCACLK_CLK_PORT_PERIPH_HANDLE),
iBSP430portBitPosition(BSP430_TIMER_CCACLK_CLK_PORT_BIT));
cprintf("Please connect TRIGGER at %s.%u to %s CCI0%c at %s.%u\n",
xBSP430portName(APP_TRIGGER_PORT_PERIPH_HANDLE),
iBSP430portBitPosition(APP_TRIGGER_PORT_BIT),
xBSP430timerName(BSP430_TIMER_CCACLK_PERIPH_HANDLE),
'A' + (APP_CC_CCIS / CCIS0),
xBSP430portName(APP_CC_PORT_PERIPH_HANDLE),
iBSP430portBitPosition(APP_CC_PORT_BIT));
/* OUTCLK: output low */
outclk = 0;
BSP430_PORT_HAL_HPL_OUT(outclk_port_hal) &= ~APP_OUTCLK_PORT_BIT;
BSP430_PORT_HAL_HPL_DIR(outclk_port_hal) |= APP_OUTCLK_PORT_BIT;
BSP430_PORT_HAL_HPL_SEL(outclk_port_hal) &= ~APP_OUTCLK_PORT_BIT;
/* TRIGGER: output low */
BSP430_PORT_HAL_HPL_OUT(trigger_port_hal) &= ~APP_TRIGGER_PORT_BIT;
BSP430_PORT_HAL_HPL_DIR(trigger_port_hal) |= APP_TRIGGER_PORT_BIT;
BSP430_PORT_HAL_HPL_SEL(trigger_port_hal) &= ~APP_TRIGGER_PORT_BIT;
/* INCLK: input peripheral function */
BSP430_PORT_HAL_HPL_SEL(inclk_port_hal) &= ~BSP430_TIMER_CCACLK_CLK_PORT_BIT;
BSP430_PORT_HAL_HPL_SEL(inclk_port_hal) |= BSP430_TIMER_CCACLK_CLK_PORT_BIT;
/* CC0: input peripheral function */
BSP430_PORT_HAL_HPL_DIR(cc_port_hal) &= ~APP_CC_PORT_BIT;
BSP430_PORT_HAL_HPL_SEL(cc_port_hal) |= APP_CC_PORT_BIT;
cprintf("P4: DIR %04x SEL %04x\n", P4DIR, P4SEL);
#define CLEAR_CAPTURE() do { \
timer_hpl->cctl[APP_CCIDX] &= ~CCIFG; \
timer_hpl->ccr[APP_CCIDX] = 0; \
} while (0)
#define ASSERT_CLOCK_HIGH() do { \
BSP430_UNITTEST_ASSERT_TRUE(BSP430_PORT_HAL_HPL_OUT(outclk_port_hal) & APP_OUTCLK_PORT_BIT); \
} while (0)
#define ASSERT_CLOCK_LOW() do { \
BSP430_UNITTEST_ASSERT_FALSE(BSP430_PORT_HAL_HPL_OUT(outclk_port_hal) & APP_OUTCLK_PORT_BIT); \
} while (0)
#define ASSERT_CCI_HIGH() do { \
BSP430_UNITTEST_ASSERT_TRUE(CCI & timer_hpl->cctl[APP_CCIDX]); \
} while (0)
#define ASSERT_CCI_LOW() do { \
BSP430_UNITTEST_ASSERT_FALSE(CCI & timer_hpl->cctl[APP_CCIDX]); \
} while (0)
#define ASSERT_INTERNAL_TRIGGER_HIGH() do { \
BSP430_UNITTEST_ASSERT_TRUE(CCIS_3 == (CCIS_3 & timer_hpl->cctl[APP_CCIDX])); \
} while (0)
#define ASSERT_INTERNAL_TRIGGER_LOW() do { \
BSP430_UNITTEST_ASSERT_TRUE(CCIS_2 == (CCIS_3 & timer_hpl->cctl[APP_CCIDX])); \
} while (0)
#define ASSERT_NO_CAPTURE() do { \
BSP430_UNITTEST_ASSERT_FALSE(CCIFG & timer_hpl->cctl[APP_CCIDX]); \
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(0, timer_hpl->ccr[APP_CCIDX]); \
} while (0)
#define ASSERT_YES_CAPTURE() do { \
BSP430_UNITTEST_ASSERT_TRUE(CCIFG & timer_hpl->cctl[APP_CCIDX]); \
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(timer_hpl->r, timer_hpl->ccr[APP_CCIDX]); \
} while (0)
/* Capture asynchronously on falling edge from TRIGGER. */
timer_hpl->ccr[APP_CCIDX] = 0;
timer_hpl->cctl[APP_CCIDX] = CM_2 | APP_CC_CCIS | SCCI | CAP;
timer_hpl->cctl[APP_CCIDX] = CM_3 | APP_CC_CCIS | SCCI | CAP;
cprintf("%u: Timer: R %04x CTL %04x CCR %04x CCTL %04x\n", __LINE__, timer_hpl->r, timer_hpl->ctl, timer_hpl->ccr[APP_CCIDX], timer_hpl->cctl[APP_CCIDX]);
/* Count upwards. */
timer_hpl->ctl = TASSEL_0 | MC_2 | TACLR;
/* Validate that we can control the clock input. */
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, 0);
ASSERT_CLOCK_LOW();
HALF_TICK_OUTCLK();
ASSERT_CLOCK_HIGH();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, 1);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
HALF_TICK_OUTCLK();
ASSERT_CLOCK_LOW();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, 1);
HALF_TICK_OUTCLK();
ASSERT_CLOCK_HIGH();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
HALF_TICK_OUTCLK();
ASSERT_CLOCK_LOW();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
/* Verify that we can control the trigger, and that asynchronous
* captures work. */
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
HALF_TRIGGER();
if (CM0 & timer_hpl->cctl[APP_CCIDX]) {
ASSERT_YES_CAPTURE();
if (! (CM1 & timer_hpl->cctl[APP_CCIDX])) {
CLEAR_CAPTURE();
}
} else {
ASSERT_NO_CAPTURE();
}
ASSERT_CCI_HIGH();
HALF_TRIGGER();
ASSERT_YES_CAPTURE();
ASSERT_CCI_LOW();
CLEAR_CAPTURE();
/* Advance the clock. Make sure no capture occurred. */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk+1);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_NO_CAPTURE();
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(last_outclk, timer_hpl->r);
ASSERT_NO_CAPTURE();
/* Now turn on synchronous capture */
timer_hpl->cctl[APP_CCIDX] |= SCS;
/* Advance the clock. Make sure no capture occurred */
cctl = timer_hpl->cctl[APP_CCIDX];
last_outclk = outclk;
ASSERT_CLOCK_LOW();
HALF_TICK_OUTCLK();
ASSERT_CLOCK_HIGH();
ASSERT_NO_CAPTURE();
HALF_TICK_OUTCLK();
ASSERT_CLOCK_LOW();
ASSERT_NO_CAPTURE();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(last_outclk+1, timer_hpl->r);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(cctl, timer_hpl->cctl[APP_CCIDX]);
/* Do this again to make really sure no capture occurred. */
HALF_TICK_OUTCLK();
ASSERT_NO_CAPTURE();
HALF_TICK_OUTCLK();
ASSERT_NO_CAPTURE();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(last_outclk+2, timer_hpl->r);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(cctl, timer_hpl->cctl[APP_CCIDX]);
/*
F1) CCI rises then falls while CLK remains low. CCIFG remains low. When CLK
rises the counter is incremented but CCIFG remains low. CCIFG is set only
when CLK falls.
*/
/* CLK is low. */
ASSERT_CLOCK_LOW();
/* Check that external triggers with sync async do not trigger when
* clock does not advance. */
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
HALF_TRIGGER();
ASSERT_NO_CAPTURE();
ASSERT_CCI_HIGH();
HALF_TRIGGER();
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
/* Advance the clock. No action on rising edge. */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk+1);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
ASSERT_CLOCK_HIGH();
/* Falling edge does not increment counter but does cause capture */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_YES_CAPTURE();
ASSERT_CCI_LOW();
CLEAR_CAPTURE();
/*
F2) CCI rises then falls while CLK remains high. CCIFG remains low. When
CLK falls CCIFG is set.
*/
/* Advance the clock. No action on rising edge. */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk+1);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
ASSERT_CLOCK_HIGH();
/* Check that external triggers with sync async do not trigger when
* clock does not advance. */
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
HALF_TRIGGER();
ASSERT_NO_CAPTURE();
ASSERT_CCI_HIGH();
HALF_TRIGGER();
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
/* Falling edge does not increment counter but does cause capture */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_YES_CAPTURE();
ASSERT_CCI_LOW();
CLEAR_CAPTURE();
/* Now test it with internal toggles. First, asynchronous: */
timer_hpl->cctl[APP_CCIDX] = CM_3 | CCIS_2 | SCCI | CAP;
ASSERT_NO_CAPTURE();
ASSERT_INTERNAL_TRIGGER_LOW();
ASSERT_CCI_LOW();
HALF_TRIGGER();
ASSERT_CCI_LOW();
ASSERT_NO_CAPTURE();
INTERNAL_HALF_TRIGGER();
ASSERT_CCI_HIGH();
ASSERT_INTERNAL_TRIGGER_HIGH();
ASSERT_YES_CAPTURE();
CLEAR_CAPTURE();
HALF_TRIGGER();
ASSERT_CCI_HIGH();
ASSERT_NO_CAPTURE();
INTERNAL_HALF_TRIGGER();
ASSERT_CCI_LOW();
ASSERT_INTERNAL_TRIGGER_LOW();
ASSERT_YES_CAPTURE();
ASSERT_CCI_LOW();
CLEAR_CAPTURE();
/* Now synchronous */
timer_hpl->cctl[APP_CCIDX] |= SCS;
ASSERT_NO_CAPTURE();
ASSERT_INTERNAL_TRIGGER_LOW();
INTERNAL_HALF_TRIGGER();
ASSERT_INTERNAL_TRIGGER_HIGH();
ASSERT_NO_CAPTURE();
INTERNAL_HALF_TRIGGER();
ASSERT_INTERNAL_TRIGGER_LOW();
ASSERT_NO_CAPTURE();
/* Advance the clock. No action on rising edge. */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk+1);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_NO_CAPTURE();
ASSERT_CCI_LOW();
ASSERT_CLOCK_HIGH();
/* Falling edge does not increment counter but does cause capture */
last_outclk = outclk;
HALF_TICK_OUTCLK();
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, last_outclk);
BSP430_UNITTEST_ASSERT_EQUAL_FMTx(outclk, timer_hpl->r);
ASSERT_YES_CAPTURE();
ASSERT_CCI_LOW();
CLEAR_CAPTURE();
cprintf("%u: Timer: R %04x CTL %04x CCR %04x CCTL %04x\n", __LINE__, timer_hpl->r, timer_hpl->ctl, timer_hpl->ccr[APP_CCIDX], timer_hpl->cctl[APP_CCIDX]);
vBSP430unittestFinalize();
}
void main ()
{
sBSP430halPORT * port_hal;
hBSP430halTIMER hal;
volatile sBSP430hplTIMER * hpl;
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cputchar('\n');
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ / 1000);
cprintf("\n\nsynccap " __DATE__ " " __TIME__ "\n");
cprintf("External input on %s.%u corresponds to %s.%u%c\n",
xBSP430portName(BSP430_TIMER_CCACLK_CC1_PORT_PERIPH_HANDLE),
bitToPin(BSP430_TIMER_CCACLK_CC1_PORT_BIT),
xBSP430timerName(BSP430_TIMER_CCACLK_PERIPH_HANDLE),
PORT_CCIDX,
'A' + (BSP430_TIMER_CCACLK_CC1_CCIS / CCIS0));
port_hal = hBSP430portLookup(BSP430_TIMER_CCACLK_CC1_PORT_PERIPH_HANDLE);
if (NULL == port_hal) {
cprintf("Port HAL not available\n");
return;
}
hal = hBSP430timerLookup(BSP430_TIMER_CCACLK_PERIPH_HANDLE);
if (NULL == hal) {
cprintf("Can't find timer\n");
return;
}
BSP430_PORT_HAL_HPL_DIR(port_hal) &= ~BSP430_TIMER_CCACLK_CC1_PORT_BIT;
BSP430_PORT_HAL_HPL_SEL(port_hal) |= BSP430_TIMER_CCACLK_CC1_PORT_BIT;
hpl = hal->hpl;
hpl->cctl[1] = CM_3 | BSP430_TIMER_CCACLK_CC1_CCIS | SCS | CAP | CCIE;
captured.last_cci = !!(hpl->cctl[1] & CCI);
BSP430_HAL_ISR_CALLBACK_LINK_NI(sBSP430halISRIndexedChainNode,
hal->cc_cbchain_ni[PORT_CCIDX],
captured.cb,
next_ni);
hpl->ctl = TASSEL_2 | MC_2 | TACLR | TAIE;
/* Need to enable interrupts so timer overflow events are properly
* acknowledged */
while (1) {
unsigned int ccr;
unsigned int cctl;
unsigned int count;
unsigned int errors;
int last_cci;
unsigned long event_tt;
BSP430_CORE_DISABLE_INTERRUPT();
do {
event_tt = captured.event_tt;
captured.event_tt = 0;
count = captured.count;
errors = captured.errors;
captured.count = 0;
captured.errors = 0;
last_cci = captured.last_cci;
cctl = hpl->cctl[PORT_CCIDX];
ccr = hpl->ccr[PORT_CCIDX];
hpl->cctl[PORT_CCIDX] &= ~COV;
} while (0);
BSP430_CORE_ENABLE_INTERRUPT();
cprintf("Up %lu ACLK ticks, timer %lu event %lx ccr %x cctl %04x\n"
"\tCCI %d SCCI %d COV %d ; recorded CCI %d ; count %u errors %d\n",
ulBSP430uptime(),
ulBSP430timerCounter(hal, NULL),
event_tt,
ccr,
cctl,
!!(cctl & CCI), !!(cctl & SCCI), !!(cctl & COV), last_cci, count, errors);
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ);
}
}
void main ()
{
volatile sBSP430hplPORTIE * b0hpl;
hBSP430halTIMER b0timer_hal;
int b0pin = iBSP430portBitPosition(BSP430_PLATFORM_BUTTON0_PORT_BIT);
struct sBSP430timerPulseCapture pulsecap_state;
hBSP430timerPulseCapture pulsecap;
unsigned long freq_Hz;
int rc;
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cprintf("\npulsecap " __DATE__ " " __TIME__ "\n");
cprintf("There's supposed to be a button at %s.%u\n",
xBSP430portName(BSP430_PLATFORM_BUTTON0_PORT_PERIPH_HANDLE),
b0pin);
b0hpl = xBSP430hplLookupPORTIE(BSP430_PLATFORM_BUTTON0_PORT_PERIPH_HANDLE);
if (NULL == b0hpl) {
cprintf("Guess it's not there. Never mind.\n");
return;
}
cprintf("Found it at %p. Now looking for timer HAL.\n", b0hpl);
b0timer_hal = hBSP430timerLookup(BUTTON0_TIMER_PERIPH_HANDLE);
if (NULL == b0timer_hal) {
cprintf("That's not there, though. Going away now.\n");
return;
}
vBSP430timerResetCounter_ni(b0timer_hal);
b0timer_hal->hpl->ctl = TASSEL__SMCLK | MC__CONTINOUS | TBCLR | TBIE;
vBSP430timerInferHints_ni(b0timer_hal);
freq_Hz = ulBSP430timerFrequency_Hz_ni(BUTTON0_TIMER_PERIPH_HANDLE);
cprintf("Cool, we're good to go with a %lu Hz timer at %p, now %lu.\n",
freq_Hz, b0timer_hal, ulBSP430timerCounter_ni(b0timer_hal, NULL));
/* Configure the port for its primary peripheral function */
b0hpl->dir &= ~BSP430_PLATFORM_BUTTON0_PORT_BIT;
BSP430_PORT_HPL_SET_REN(b0hpl, BSP430_PLATFORM_BUTTON0_PORT_BIT, BSP430_PORT_REN_PULL_UP);
BSP430_PORT_HPL_SET_SEL(b0hpl, BSP430_PLATFORM_BUTTON0_PORT_BIT, 1);
pulsecap = hBSP430timerPulseCaptureInitialize(&pulsecap_state,
BUTTON0_TIMER_PERIPH_HANDLE,
BUTTON0_TIMER_CCIDX,
BUTTON0_TIMER_CCIS,
BSP430_TIMER_PULSECAP_START_CALLBACK | BSP430_TIMER_PULSECAP_END_CALLBACK,
pulsecap_callback_ni);
if (NULL == pulsecap) {
cprintf("Sorry, pulsecap initialization failed\n");
return;
}
cprintf("%s.%u%c cctl %04x; pulsecap %p flags %04x\n",
xBSP430timerName(BUTTON0_TIMER_PERIPH_HANDLE),
BUTTON0_TIMER_CCIDX,
'A' + (BUTTON0_TIMER_CCIS / CCIS0),
b0timer_hal->hpl->cctl[BUTTON0_TIMER_CCIDX],
pulsecap, pulsecap->flags_ni);
/* Need to enable interrupts so timer overflow events are properly
* acknowledged */
BSP430_CORE_ENABLE_INTERRUPT();
rc = iBSP430timerPulseCaptureEnable(pulsecap);
cprintf("Enable got %d\n", rc);
rc = iBSP430timerPulseCaptureActivate(pulsecap);
cprintf("Activate got %d\n", rc);
while (1) {
unsigned int flags;
unsigned long pulseWidth_tt;
unsigned int overflows;
unsigned int activehighs;
BSP430_CORE_DISABLE_INTERRUPT();
do {
flags = pulsecap_state.flags_ni;
pulseWidth_tt = pulseWidth_tt_v;
overflows = overflows_v;
activehighs = activehighs_v;
} while (0);
BSP430_CORE_ENABLE_INTERRUPT();
cprintf("Timer %lu flags %04x ; %u over %u activehigh\n",
ulBSP430timerCounter(b0timer_hal, NULL),
flags, overflows, activehighs);
if (0 != pulseWidth_tt) {
cprintf("\tNew width: %lu ticks = %lu us\n", pulseWidth_tt,
(unsigned long)((1000ULL * pulseWidth_tt) / (freq_Hz / 1000UL)));
pulseWidth_tt = 0;
}
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ);
}
}