//*****************************************************************************
//
//! \brief xspi 004 test of SPI interrupt register.
//!
//! \return None.
//
//*****************************************************************************
static void xspi004_IntRegister_test(void)
{
unsigned long i, j, ulRegVal;
for(i = 0; i < 2; i++)
{
for(j = 0; j < 3; j++)
{
SPIIntEnable(ulSPI[i],ulIntFlags[j]);
ulRegVal = xHWREGB(ulSPI[i] + SPI_C1) & (ulIntFlags[j] << 4);
TestAssert(ulRegVal == (unsigned char)(ulIntFlags[j] << 4), "xspi API error!");
}
for(j = 3; j < 5; j++)
{
SPIIntEnable(ulSPI[i], ulIntFlags[j]);
ulRegVal = xHWREGB(ulSPI[i] + SPI_C2) & (ulIntFlags[j] << 4);
TestAssert(ulRegVal == (unsigned char)(ulIntFlags[j] << 4), "xspi API error!");
}
for(j = 0; j < 3; j++)
{
SPIIntDisable(ulSPI[i],ulIntFlags[j]);
ulRegVal = xHWREGB(ulSPI[i] + SPI_C1) & (ulIntFlags[j] << 4);
TestAssert(ulRegVal == 0, "xspi API error!");
}
for(j = 3; j < 5; j++)
{
SPIIntDisable(ulSPI[i],ulIntFlags[j]);
ulRegVal = xHWREGB(ulSPI[i] + SPI_C2) & (ulIntFlags[j] << 4);
TestAssert(ulRegVal == 0, "xspi API error!");
}
}
}
void ACMPConfigure(unsigned long ulBase, unsigned long ulCompID, unsigned long ulConfig)
{
unsigned long ulCRAddr;
unsigned long ulPlus;
unsigned long ulMinus;
xASSERT(ulBase == ACMP_BASE);
xASSERT((ulCompID >= 0) && (ulCompID < 2));
//
// Get the corresponding CR register address
//
ulCRAddr = ulBase + CMP0_MUXCR + (4 * ulCompID);
if(((ulConfig & CMP0_MUXCR_PSEL_M) == CMP0_MUXCR_PSEL_M) ||
((ulConfig & CMP0_MUXCR_MSEL_M) == CMP0_MUXCR_MSEL_M));
{
xHWREGB(ulBase + CMP0_DACCR) |= CMP0_DACCR_DACEN;
}
//
// Set the comp- input source
//
ulPlus = (ulConfig & CMP0_MUXCR_PSEL_M);
xHWREGB(ulCRAddr) &= ~CMP0_MUXCR_PSEL_M;
xHWREGB(ulCRAddr) |= ulPlus;
ulMinus = (ulConfig & CMP0_MUXCR_MSEL_M);
xHWREGB(ulCRAddr) &= ~CMP0_MUXCR_MSEL_M;
xHWREGB(ulCRAddr) |= ulMinus;
}
unsigned long USART1IntHandler(void *pvCBData,
unsigned long ulEvent,
unsigned long ulMsgParam,
void *pvMsgData)
{
char receive_byte;
if ((ulEvent & UART_EVENT_RX) == UART_EVENT_RX)
{
receive_byte = xHWREGB(UART1_BASE + UART_012_D);
if (OSQueuePost(Serial1, receive_byte) == BUFFER_UNDERRUN)
{
// Problema: Estouro de buffer
//OSCleanQueue(Serial0);
}
}
if ((ulEvent & UART_EVENT_TC) == UART_EVENT_TC)
{
if ((xHWREGB(UART1_BASE + UART_012_C2) & UART_EVENT_TC) == UART_EVENT_TC)
{
UARTIntDisable(UART1_BASE, UART_INT_TC);
(void)OSSemPost(SerialTX1);
}
}
// ************************
// Interrupt Exit
// ************************
OS_INT_EXIT_EXT();
// ************************
return 0;
}
unsigned long USART0IntHandler(void *pvCBData,
unsigned long ulEvent,
unsigned long ulMsgParam,
void *pvMsgData)
{
char receive_byte;
if (Contiki_Sem != NULL){
if ((ulEvent & UART_EVENT_RX) == UART_EVENT_RX)
{
receive_byte = xHWREGB(UART0_BASE + UART_012_D);
if (slip_input_byte(receive_byte) == 1) OSSemPost(Contiki_Sem);
buffer_rcvd[buffer_rcvd_i++]=receive_byte;
#if 0
if (OSQueuePost(Serial0, receive_byte) == BUFFER_UNDERRUN)
{
// Problema: Estouro de buffer
OSQueueClean(Serial0);
}
#endif
}
if ((ulEvent & UART_EVENT_TC) == UART_EVENT_TC)
{
if ((xHWREGB(UART0_BASE + UART_012_C2) & UART_EVENT_TC) == UART_EVENT_TC)
{
UARTIntDisable(UART0_BASE, UART_INT_TC);
(void)OSSemPost(SerialTX0);
}
}
// ************************
// Interrupt Exit
// ************************
OS_INT_EXIT_EXT();
// ************************
}else{
if ((ulEvent & UART_EVENT_RX) == UART_EVENT_RX)
{
receive_byte = xHWREGB(UART0_BASE + UART_012_D);
}
if ((ulEvent & UART_EVENT_TC) == UART_EVENT_TC)
{
if ((xHWREGB(UART0_BASE + UART_012_C2) & UART_EVENT_TC) == UART_EVENT_TC)
{
UARTIntDisable(UART0_BASE, UART_INT_TC);
}
}
}
}
//*****************************************************************************
//
//! \brief Clear a comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index(0 - 1) of the comparator.
//!
//! The comparator interrupt is cleared, so that it no longer asserts. This
//! fucntion must be called in the interrupt handler to keep the handler from
//! being called again immediately upon exit.
//!
//! \note In KL25Z Series, the ulComp must be 0.
//!
//! \return None.
//
//*****************************************************************************
void
ACMPIntClear(unsigned long ulBase, unsigned long ulComp)
{
xASSERT(ulBase == ACMP_BASE);
xASSERT((ulComp >= 0) && (ulComp < 2));
//
// Wirte 1 to clear the comp flag
//
ulComp +=0;
xHWREGB(ulBase + CMP0_SCR) |= CMP0_SCR_CFF;
xHWREGB(ulBase + CMP0_SCR) |= CMP0_SCR_CFR;
}
//*****************************************************************************
//
//! \brief set the SPI clock status when the MCU enters wait mode.
//!
//! \param ulBase specifies the SPI module base address.
//! \param ulMode specifies the SPI clock status in wait mode.
//!
//! This function is to set the SPI clock continue when the MCU enters wait mode.
//!
//! The \e ulMode can be one of the following values:
//! \b SPI_CLK_STOP or \b SPI_CLK_CONTINUE.
//!
//! \note This bit is used for power conservation while the device is in
//! wait mode.
//!
//! \return None.
//
//*****************************************************************************
void
SPIClkStatusForWaitMode(unsigned long ulBase, unsigned long ulMode)
{
//
// Check the arguments.
//
xASSERT((ulBase == SPI0_BASE) || (ulBase == SPI1_BASE));
xHWREGB(ulBase + SPI_C2) &= ~SPI_C2_SPISWAI;
if(ulMode == SPI_CLK_STOP)
{
xHWREGB(ulBase + SPI_C2) |= SPI_C2_SPISWAI;
}
}
//*****************************************************************************
//
//! \brief Set CMP Filter Sample Period.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulPeriod is the CMP Filter Sample Period.
//!
//! This function to Set Filter Sample Period.
//!
//! \note This function has no effect when Sampling mode is selected(CR1[SE]=1).
//! In that case, the external SAMPLE signal is used to determine the sampling
//! period.
//!
//! \return None.
//
//*****************************************************************************
void
CMPFilterSamplePeriodSet(unsigned long ulBase, unsigned long ulPeriod)
{
//
// Check the arguments
//
xASSERT(ulBase == ACMP_BASE);
//
// Set CMP Filter Sample Period
//
xHWREGB(ulBase + CMP0_FPR) &= ~CMP0_FPR_FILT_PER_M;
xHWREGB(ulBase + CMP0_FPR) |= ulPeriod;
}
//*****************************************************************************
//
//! \brief Set DAC Output Voltage.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulVoltage is the DAC Output Voltage that you will set.
//!
//! This function to Set DAC Output Voltage.
//!
//! \return None.
//
//*****************************************************************************
void
CMPDACOutputVoltageSet(unsigned long ulBase, unsigned long ulVoltage)
{
//
// Check the arguments
//
xASSERT(ulBase == ACMP_BASE);
xASSERT((ulVoltage >= 0) && (ulVoltage < 64));
//
// Set DAC Output Voltage
//
xHWREGB(ulBase + CMP0_DACCR) &= ~CMP0_DACCR_VOSEL_M;
xHWREGB(ulBase + CMP0_DACCR) |= ulVoltage;
}
//*****************************************************************************
//
//! \brief Set the slave select pins of the specified SPI port.
//!
//! \param ulBase specifies the SPI module base address.
//! \param ulSlaveSel specifies the slave select output enable.
//!
//! This function is to Set the slave select pins of the
//! specified SPI port.
//!
//! The \e ulSlaveSel can be one of the following values:
//! \b SPI_SS_MODEFAULT or \b SPI_SS_OUTPUT.
//!
//! \note this is only for master
//!
//! \return None.
//
//*****************************************************************************
void
SPISSSet(unsigned long ulBase, unsigned long ulSlaveSel)
{
//
// Check the arguments.
//
xASSERT((ulBase == SPI0_BASE) || (ulBase == SPI1_BASE));
xHWREGB(ulBase + SPI_C2) |= SPI_C2_MODFEN;
xHWREGB(ulBase + SPI_C1) &= ~SPI_C1_SSOE;
if(ulSlaveSel == SPI_SS_OUTPUT)
{
xHWREGB(ulBase + SPI_C1) |= SPI_C1_SSOE;
}
}
xtBoolean UARTPutString(unsigned long ulBase, char *string)
{
INT8U result = 0;
while(*string)
{
xHWREGB(ulBase + UART_012_D) = *string;
UARTIntEnable(ulBase, UART_INT_TC);
if (ulBase == UART0_BASE)
{
result = OSSemPend(SerialTX0,5);
}
if (ulBase == UART1_BASE)
{
result = OSSemPend(SerialTX1,5);
}
if (ulBase == UART2_BASE)
{
result = OSSemPend(SerialTX2,5);
}
string++;
}
return result;
}
//*****************************************************************************
//
//! \brief Configures the synchronous serial interface.
//!
//! \param ulBase specifies the SPI module base address.
//! \param ulSPIClk is the rate of the clock supplied to the SPI module.
//! \param ulProtocol specifies the data transfer protocol.
//! \param ulMode specifies the mode of operation.
//! \param ulBitRate specifies the clock rate.
//! \param ulShiftDirection specifies direction of bits transferred per frame.
//!
//! This function configures the synchronous serial interface. It sets
//! the SPI protocol, mode of operation, bit rate, and data shift direction.
//!
//! The \e ulProtocol parameter defines the data frame format. The
//! \e ulProtocol parameter can be one of the following values:
//! \b SPI_FRF_MOTO_MODE_0, \b SPI_FRF_MOTO_MODE_1, \b SPI_FRF_MOTO_MODE_2,
//! \b SPI_FRF_MOTO_MODE_3.
//! The Motorola frame formats imply the following polarity and phase
//! configurations:
//!
//! <pre>
//! Polarity Phase Mode
//! 0 0 SPI_FRF_MOTO_MODE_0
//! 0 1 SPI_FRF_MOTO_MODE_1
//! 1 0 SPI_FRF_MOTO_MODE_2
//! 1 1 SPI_FRF_MOTO_MODE_3
//! </pre>
//!
//! The \e ulMode parameter defines the operating mode of the SPI module. The
//! SPI module can operate as a master or slave; if a slave, the SPI can be
//! configured to disable output on its serial output line. The \e ulMode
//! parameter can be one of the following values: \b SPI_MODE_MASTER,
//! \b SPI_MODE_SLAVE, or \b SPI_MODE_SLAVE_OD.
//!
//! The \e ulBitRate parameter defines the bit rate for the SPI. This bit rate
//! must satisfy the following clock ratio criteria:
//!
//! - FSPI >= 2 * bit rate (master mode)
//! - FSPI >= 12 * bit rate (slave modes)
//!
//! where FSPI is the frequency of the clock supplied to the SPI module.
//!
//! The \e ulShiftDirection parameter defines the direction of the data
//! transfers.
//!
//! The peripheral clock will be the same as the processor clock. This will be
//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtlClockGet()).
//!
//! This function replaces the original SPIConfig() API and performs the same
//! actions. A macro is provided in <tt>spi.h</tt> to map the original API to
//! this API.
//!
//! \return None.
//
//*****************************************************************************
void
SPIConfigSetExpClk(unsigned long ulBase, unsigned long ulSPIClk,
unsigned long ulProtocol, unsigned long ulMode,
unsigned long ulBitRate, unsigned long ulShiftDirection)
{
unsigned long ulMaxBitRate;
unsigned long ulRegVal;
unsigned long ulPreDiv;
unsigned long ulSCR;
unsigned long ulCnt;
//
// Check the arguments.
//
xASSERT((ulBase == SPI0_BASE) || (ulBase == SPI1_BASE));
xASSERT((ulProtocol == SPI_FRF_MOTO_MODE_0) ||
(ulProtocol == SPI_FRF_MOTO_MODE_1) ||
(ulProtocol == SPI_FRF_MOTO_MODE_2) ||
(ulProtocol == SPI_FRF_MOTO_MODE_3));
xASSERT((ulMode == SPI_MODE_MASTER) || (ulMode == SPI_MODE_SLAVE));
xASSERT(((ulMode == SPI_MODE_MASTER) && (ulBitRate <= (ulSPIClk / 2))) ||
((ulMode == SPI_MODE_SLAVE) && (ulBitRate <= (ulSPIClk / 4))));
xASSERT((ulSPIClk / ulBitRate) <= (512 * 8));
//
// Set the clock predivider.
//
ulMaxBitRate = ulSPIClk / ulBitRate;
ulPreDiv = 1;
ulCnt = 0;
do
{
ulCnt ++;
ulPreDiv *= 2;
ulSCR = ulMaxBitRate / ulPreDiv;
}
while(ulSCR > 8);
xHWREGB(ulBase + SPI_BR) = (unsigned char)(ulCnt - 1);
xHWREGB(ulBase + SPI_BR) |= (unsigned char)((ulSCR - 1) << SPI_BR_SPPR_S);
//
// Set protocol
//
ulRegVal = (ulShiftDirection | ulMode | ulProtocol);
xHWREGB(ulBase + SPI_C1) = (unsigned char)ulRegVal;
}
//*****************************************************************************
//
//! \brief Enable/disable the 3 wire feature of the specified SPI port.
//!
//! \param ulBase specifies the SPI module base address.
//! \param ulMode specifies the SPI is configured as a master or a slave,
//! it uses the MOSI (MOMI) or MISO (SISO) pin.
//!
//! This function enable the 3 wire feature. the controller start to transmit/
//!receive data after the GO_BUSY bit active and the serial clock input.
//!
//! In no slave select signal mode, the BIDIROE, SPI_C2[3], shuld be
//! set as 1.
//!
//! \return None.
//
//*****************************************************************************
void
SPI3WireEnable(unsigned long ulBase, unsigned long ulMode)
{
//
// Check the arguments.
//
xASSERT((ulBase == SPI0_BASE) || (ulBase == SPI1_BASE));
xASSERT((ulMode == SPI_MODE_MASTER) || (ulMode == SPI_MODE_SLAVE));
xHWREGB(ulBase + SPI_C2) |= SPI_C2_SPC0;
xHWREGB(ulBase + SPI_C2) &= ~SPI_C2_BIDIROE;
if(ulMode == SPI_MODE_MASTER)
{
xHWREGB(ulBase + SPI_C2) |= SPI_C2_BIDIROE;
}
}
//*****************************************************************************
//
//! \brief Set CMP0 Comparator hard block hysteresis control.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulLevel is the the programmable hysteresis level.
//!
//! This function is used to Set Comparator hard block hysteresis control.
//!
//! \return None.
//
//*****************************************************************************
void
CMPHystersisLevelSet(unsigned long ulBase, unsigned long ulLevel)
{
//
// Check the arguments
//
xASSERT(ulBase == ACMP_BASE);
xASSERT((ulLevel == CMP_HYSTERESIS_LEVEL_0)||
(ulLevel == CMP_HYSTERESIS_LEVEL_1)||
(ulLevel == CMP_HYSTERESIS_LEVEL_2)||
(ulLevel == CMP_HYSTERESIS_LEVEL_3));
//
// Set hysteresis level
//
xHWREGB(ulBase + CMP0_CR0) &= ~CMP0_CR0_HYSTCTR_M;
xHWREGB(ulBase + CMP0_CR0) |= ulLevel;
}
//*****************************************************************************
//
//! \brief Clear the slave select pins of the specified SPI port.
//!
//! \param ulBase specifies the SPI module base address.
//!
//! This function is to Clear the slave select pins of the
//! specified SPI port.
//!
//! \note this is only for master
//!
//! \return None.
//
//*****************************************************************************
void
SPISSClear(unsigned long ulBase)
{
//
// Check the arguments.
//
xASSERT((ulBase == SPI0_BASE) || (ulBase == SPI1_BASE));
xHWREGB(ulBase + SPI_C2) &= ~SPI_C2_MODFEN;
}
//*****************************************************************************
//
//! \brief Abort transfer when using 3-wire SPI.
//!
//! \param ulBase specifies the SPI module base address.
//!
//! This function abort transfer when using 3-wire SPI. If using 3-wire SPI as
//! slave, when slave start interrupt status is set but transfer done flag
//! doesn't be set over a reasonable time, use this function to abort this
//! transfer.
//!
//! \return None.
//
//*****************************************************************************
void
SPI3WireDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
xASSERT((ulBase == SPI0_BASE) || (ulBase == SPI1_BASE));
xHWREGB(ulBase + SPI_C2) &= ~SPI_C2_SPC0;
}
//*****************************************************************************
//
//! \brief Set CMP0 Plus and Minus Comparator Input Mux.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulPlus is the the Plus Input Mux.
//! \param ulMinus is the the Minus Input Mux.
//!
//! This function is used to Set Comparator Plus and Minus Comparator Input Mux.
//!
//! \note You must Enable DAC before you set the ulPlus or ulMinus is 7.
//!
//! \return None.
//
//*****************************************************************************
void
CMPInputMuxSet(unsigned long ulBase, unsigned long ulPlus, unsigned long ulMinus)
{
//
// Check the arguments
//
xASSERT(ulBase == ACMP_BASE);
xASSERT((ulPlus >= 0) && (ulPlus < 8));
xASSERT((ulMinus >= 0) && (ulMinus < 8));
//
// Set CMP0 Plus and Minus Comparator Input Mux.
//
xHWREGB(ulBase + CMP0_MUXCR) &= ~CMP0_MUXCR_PSEL_M;
xHWREGB(ulBase + CMP0_MUXCR) |= (ulPlus << CMP0_MUXCR_PSEL_S);
xHWREGB(ulBase + CMP0_MUXCR) &= ~CMP0_MUXCR_MSEL_M;
xHWREGB(ulBase + CMP0_MUXCR) |= (ulMinus << CMP0_MUXCR_MSEL_S);
}
//*****************************************************************************
//
//! \brief Disable the comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulCompID is the index(0 - 1) of the comparator.
//!
//! This function disables generation of an interrupt from the specified
//! comparator. Only comparators whose interrupts are enabled can be reflected
//! to the processor.
//!
//! \note In KL25Z Series, the ulCompID must be 0.
//!
//! \return None.
//
//*****************************************************************************
void
ACMPIntDisable(unsigned long ulBase, unsigned long ulCompID)
{
unsigned long ulCRAddr;
xASSERT(ulBase == ACMP_BASE);
xASSERT((ulCompID >= 0) && (ulCompID < 2));
//
// Get the corresponding CR register address
//
ulCRAddr = ulBase + CMP0_SCR + (4 * ulCompID);
//
// Disable the comparator interrupt
//
xHWREGB(ulCRAddr) &= ~CMP0_SCR_IEF;
xHWREGB(ulCRAddr) &= ~CMP0_SCR_IER;
}
//*****************************************************************************
//
//! \brief Disable the DAC of ACMP.
//!
//! \param ulBase is the base address of the comparator module.
//!
//! This function Disables the DAC of ACMP.
//!
//! \return None.
//
//*****************************************************************************
void
ACMPDACDisable(unsigned long ulBase)
{
xASSERT(ulBase == ACMP_BASE);
//
// Enable the DAC of ACMP.
//
xHWREGB(ulBase + CMP0_DACCR) &= ~CMP0_DACCR_DACEN;
}
//*****************************************************************************
//
//! \brief Enable the Comparator Output Pin.
//!
//! \param ulBase is the base address of the comparator module.
//!
//! This function enables Comparator Output Pin.
//!
//! \return None.
//
//*****************************************************************************
void
ACMPComparatorOutputPinEnable(unsigned long ulBase)
{
xASSERT(ulBase == ACMP_BASE);
//
// Enable the Comparator Output Pin.
//
xHWREGB(ulBase + CMP0_CR1) |= CMP0_CR1_OPE;
}
//*****************************************************************************
//
//! \brief Disable Pass Through Mode.
//!
//! \param ulBase is the base address of the comparator module.
//!
//! This function disables Pass Through Mode.
//!
//! \return None.
//
//*****************************************************************************
void
ACMPPassThroughModeDisable(unsigned long ulBase)
{
xASSERT(ulBase == ACMP_BASE);
//
// Disable the comparator Pass Through Mode.
//
xHWREGB(ulBase + CMP0_MUXCR) &= ~CMP0_MUXCR_PSTM;
}
//*****************************************************************************
//
//! \brief Disable the Comparator INVERT.
//!
//! \param ulBase is the base address of the comparator module.
//!
//! This function Disables INVERT.
//!
//! \return None.
//
//*****************************************************************************
void
ACMPInvertDisable(unsigned long ulBase)
{
xASSERT(ulBase == ACMP_BASE);
//
// Disable the Comparator Output Pin.
//
xHWREGB(ulBase + CMP0_CR1) &= ~CMP0_CR1_INV;
}
//*****************************************************************************
//
//! \brief Disable the comparator Trigger Mode.
//!
//! \param ulBase is the base address of the comparator module.
//!
//! This function disables Trigger Mode.
//!
//! \return None.
//
//*****************************************************************************
void
ACMPTriggerModeDisable(unsigned long ulBase)
{
xASSERT(ulBase == ACMP_BASE);
//
// Enable the comparator Trigger function.
//
xHWREGB(ulBase + CMP0_CR1) &= ~CMP0_CR1_TRIGM;
}
//*****************************************************************************
//
//! \brief Disable the comparator Windowing.
//!
//! \param ulBase is the base address of the comparator module.
//!
//! This function Disables Windowing function.
//!
//! \return None.
//
//*****************************************************************************
void
ACMPWindowingModeDisable(unsigned long ulBase)
{
xASSERT(ulBase == ACMP_BASE);
//
// Disable the comparator Windowing function.
//
xHWREGB(ulBase + CMP0_CR1) &= ~CMP0_CR1_WE;
}
//*****************************************************************************
//
//! \brief Disable the comparator Sample.
//!
//! \param ulBase is the base address of the comparator module.
//!
//! This function disables sample function.
//!
//! \return None.
//
//*****************************************************************************
void
ACMPSampleDisable(unsigned long ulBase)
{
xASSERT(ulBase == ACMP_BASE);
//
// Disable the comparator sample function.
//
xHWREGB(ulBase + CMP0_CR1) &= ~CMP0_CR1_SE;
}
//*****************************************************************************
//
//! \brief Disables individual SPI interrupt sources.
//!
//! \param ulBase specifies the SPI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated SPI interrupt sources. The \e ulIntFlags parameter
//! can be any of the \b SPI_SPRF, \b SPI_MODF, \b SPI_SPTEF, or \b SPI_SPMF
//! or \b SPI_SPLPF values.
//!
//! \return None.
//
//*****************************************************************************
void
SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
xASSERT((ulBase == SPI0_BASE) || (ulBase == SPI1_BASE));
//
// Disable the specified interrupts.
//
if(ulIntFlags & 0xF0)
{
xHWREGB(ulBase + SPI_C2) &= ~((unsigned char)(ulIntFlags << 4));
}
else
{
xHWREGB(ulBase + SPI_C1) &= ~((unsigned char)(ulIntFlags << 4));
}
}
//*****************************************************************************
//
//! \brief Gets a data element from the SPI receive FIFO.
//!
//! \param ulBase specifies the SPI module base address.
//! \param pulData is a pointer to a storage location for data that was
//! received over the SPI interface.
//!
//! This function gets received data from the receive FIFO of the specified
//! SPI module and places that data into the location specified by the
//! \e pulData parameter.
//!
//! \note The data width is always 8-bit.
//!
//! \return None.
//
//*****************************************************************************
void
SPIDataGet(unsigned long ulBase, unsigned long *pulData)
{
//
// Check the arguments.
//
xASSERT((ulBase == SPI0_BASE) || (ulBase == SPI1_BASE));
//
// Wait until there is data to be read.
//
while(!(xHWREGB(ulBase + SPI_S) & SPI_S_SPRF))
{
}
//
// Read data from SPI.
//
*pulData = xHWREGB(ulBase + SPI_D);
}
//*****************************************************************************
//
//! \brief Puts a data element into the SPI transmit .
//!
//! \param ulBase specifies the SPI module base address.
//! \param ulData is the data to be transmitted over the SPI interface.
//!
//! This function places the supplied data into the transmit buffer of the
//! specified SPI module.
//!
//! \note The data width is always 8-bit.
//!
//! \return None.
//
//*****************************************************************************
void
SPIDataPut(unsigned long ulBase, unsigned long ulData)
{
//
// Check the arguments.
//
xASSERT((ulBase == SPI0_BASE) || (ulBase == SPI1_BASE));
xASSERT(ulData < 256);
//
// Wait until SPRF is set.
//
while(!(xHWREGB(ulBase + SPI_S) & SPI_S_SPTEF))
{
}
//
// Write the data to the SPI.
//
xHWREGB(ulBase + SPI_D) = (unsigned char)ulData;
}
//*****************************************************************************
//
//! \brief Gets a data element from the SPI receive FIFO.
//!
//! \param ulBase specifies the SPI module base address.
//! \param pulData is a pointer to a storage location for data that was
//! received over the SPI interface.
//!
//! This function gets received data from the receive FIFO of the specified SPI
//! module and places that data into the location specified by the \e ulData
//! parameter. If there is no data in the FIFO, then this function returns a
//! zero.
//!
//! This function replaces the original SPIDataNonBlockingGet() API and
//! performs the same actions. A macro is provided in <tt>spi.h</tt> to map
//! the original API to this API.
//!
//! \note The data width is always 8-bit.
//!
//! \return Returns the number of elements read from the SPI receive FIFO.
//
//*****************************************************************************
long
SPIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
{
//
// Check the arguments.
//
xASSERT((ulBase == SPI0_BASE) || (ulBase == SPI1_BASE));
//
// Check for data to read.
//
if(xHWREGB(ulBase + SPI_S) & SPI_S_SPRF)
{
*pulData = xHWREGB(ulBase + SPI_D);
return(1);
}
else
{
return(0);
}
}
//*****************************************************************************
//
//! \brief Disable the comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulIntType is the Interrupt Type.
//!
//! This function disables generation of an interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
ACMPIntDisable2(unsigned long ulBase, unsigned long ulIntType)
{
xASSERT(ulBase == ACMP_BASE);
xASSERT((ulIntType == ACMP_INT_RISING) ||
(ulIntType == ACMP_INT_FALLING) ||
(ulIntType == (ACMP_INT_FALLING|ACMP_INT_RISING)));
//
// Disable the comparator interrupt
//
xHWREGB(ulBase + CMP0_SCR) &= ~ulIntType;
}
//*****************************************************************************
//
//! \brief Disable CMP DMA.
//!
//! \param ulBase is the base address of the CMP port.
//!
//! \return None.
//
//*****************************************************************************
void
CMPDMADisable(unsigned long ulBase)
{
//
// Check the arguments.
//
xASSERT(ulBase == ACMP_BASE);
//
// Disable DMA for CMP
//
xHWREGB(ulBase + CMP0_SCR) &= ~CMP0_SCR_DMAEN;
}
