/* create a plane */
static struct xilinx_drm_plane *
xilinx_drm_plane_create(struct xilinx_drm_plane_manager *manager,
unsigned int possible_crtcs, bool primary)
{
struct xilinx_drm_plane *plane;
struct device *dev = manager->drm->dev;
char name[16];
struct device_node *plane_node;
struct device_node *sub_node;
enum drm_plane_type type;
uint32_t fmt_in = -1;
uint32_t fmt_out = -1;
const char *fmt;
int i;
int ret;
for (i = 0; i < manager->num_planes; i++)
if (!manager->planes[i])
break;
if (i >= manager->num_planes) {
DRM_ERROR("failed to allocate plane\n");
return ERR_PTR(-ENODEV);
}
snprintf(name, sizeof(name), "plane%d", i);
plane_node = of_get_child_by_name(manager->node, name);
if (!plane_node) {
DRM_ERROR("failed to find a plane node\n");
return ERR_PTR(-ENODEV);
}
plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
if (!plane) {
ret = -ENOMEM;
goto err_out;
}
plane->primary = primary;
plane->id = i;
plane->prio = i;
plane->zpos = i;
plane->alpha = manager->default_alpha;
plane->dpms = DRM_MODE_DPMS_OFF;
plane->format = -1;
DRM_DEBUG_KMS("plane->id: %d\n", plane->id);
for (i = 0; i < MAX_NUM_SUB_PLANES; i++) {
snprintf(name, sizeof(name), "dma%d", i);
plane->dma[i].chan = of_dma_request_slave_channel(plane_node,
name);
if (PTR_ERR(plane->dma[i].chan) == -ENODEV) {
plane->dma[i].chan = NULL;
continue;
}
if (IS_ERR(plane->dma[i].chan)) {
DRM_ERROR("failed to request dma channel\n");
ret = PTR_ERR(plane->dma[i].chan);
plane->dma[i].chan = NULL;
goto err_dma;
}
}
/* probe color space converter */
sub_node = of_parse_phandle(plane_node, "xlnx,rgb2yuv", i);
if (sub_node) {
plane->rgb2yuv = xilinx_rgb2yuv_probe(dev, sub_node);
of_node_put(sub_node);
if (IS_ERR(plane->rgb2yuv)) {
DRM_ERROR("failed to probe a rgb2yuv\n");
ret = PTR_ERR(plane->rgb2yuv);
goto err_dma;
}
/* rgb2yuv input format */
plane->format = DRM_FORMAT_XRGB8888;
/* rgb2yuv output format */
fmt_out = DRM_FORMAT_YUV444;
}
/* probe chroma resampler */
sub_node = of_parse_phandle(plane_node, "xlnx,cresample", i);
if (sub_node) {
plane->cresample = xilinx_cresample_probe(dev, sub_node);
of_node_put(sub_node);
if (IS_ERR(plane->cresample)) {
DRM_ERROR("failed to probe a cresample\n");
ret = PTR_ERR(plane->cresample);
goto err_dma;
}
/* cresample input format */
fmt = xilinx_cresample_get_input_format_name(plane->cresample);
ret = xilinx_drm_format_by_name(fmt, &fmt_in);
if (ret)
goto err_dma;
/* format sanity check */
if ((fmt_out != -1) && (fmt_out != fmt_in)) {
DRM_ERROR("input/output format mismatch\n");
ret = -EINVAL;
goto err_dma;
}
if (plane->format == -1)
plane->format = fmt_in;
/* cresample output format */
fmt = xilinx_cresample_get_output_format_name(plane->cresample);
ret = xilinx_drm_format_by_name(fmt, &fmt_out);
if (ret)
goto err_dma;
}
/* create an OSD layer when OSD is available */
if (manager->osd) {
/* format sanity check */
if ((fmt_out != -1) && (fmt_out != manager->format)) {
DRM_ERROR("input/output format mismatch\n");
ret = -EINVAL;
goto err_dma;
}
/* create an osd layer */
plane->osd_layer = xilinx_osd_layer_get(manager->osd);
if (IS_ERR(plane->osd_layer)) {
DRM_ERROR("failed to create a osd layer\n");
ret = PTR_ERR(plane->osd_layer);
plane->osd_layer = NULL;
goto err_dma;
}
if (plane->format == -1)
plane->format = manager->format;
}
if (manager->dp_sub) {
plane->dp_layer = xilinx_drm_dp_sub_layer_get(manager->dp_sub,
primary);
if (IS_ERR(plane->dp_layer)) {
DRM_ERROR("failed to create a dp_sub layer\n");
ret = PTR_ERR(plane->dp_layer);
plane->dp_layer = NULL;
goto err_dma;
}
if (primary) {
ret = xilinx_drm_dp_sub_layer_set_fmt(manager->dp_sub,
plane->dp_layer,
manager->format);
if (ret) {
DRM_ERROR("failed to set dp_sub layer fmt\n");
goto err_dma;
}
}
plane->format =
xilinx_drm_dp_sub_layer_get_fmt(manager->dp_sub,
plane->dp_layer);
}
/* If there's no IP other than VDMA, pick the manager's format */
if (plane->format == -1)
plane->format = manager->format;
/* initialize drm plane */
type = primary ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
ret = drm_universal_plane_init(manager->drm, &plane->base,
possible_crtcs, &xilinx_drm_plane_funcs,
&plane->format, 1, type, NULL);
if (ret) {
DRM_ERROR("failed to initialize plane\n");
goto err_init;
}
plane->manager = manager;
manager->planes[plane->id] = plane;
xilinx_drm_plane_attach_property(&plane->base);
of_node_put(plane_node);
return plane;
err_init:
if (manager->dp_sub) {
xilinx_drm_dp_sub_layer_disable(manager->dp_sub,
plane->dp_layer);
xilinx_drm_dp_sub_layer_put(plane->manager->dp_sub,
plane->dp_layer);
}
if (manager->osd) {
xilinx_osd_layer_disable(plane->osd_layer);
xilinx_osd_layer_put(plane->osd_layer);
}
err_dma:
for (i = 0; i < MAX_NUM_SUB_PLANES; i++)
if (plane->dma[i].chan)
dma_release_channel(plane->dma[i].chan);
err_out:
of_node_put(plane_node);
return ERR_PTR(ret);
}
/* create crtc */
struct drm_crtc *xilinx_drm_crtc_create(struct drm_device *drm)
{
struct xilinx_drm_crtc *crtc;
struct device_node *sub_node;
int possible_crtcs = 1;
int ret;
crtc = devm_kzalloc(drm->dev, sizeof(*crtc), GFP_KERNEL);
if (!crtc)
return ERR_PTR(-ENOMEM);
/* probe chroma resampler and enable */
sub_node = of_parse_phandle(drm->dev->of_node, "cresample", 0);
if (sub_node) {
crtc->cresample = xilinx_cresample_probe(drm->dev, sub_node);
of_node_put(sub_node);
if (IS_ERR(crtc->cresample)) {
DRM_ERROR("failed to probe a cresample\n");
return ERR_CAST(crtc->cresample);
}
}
/* probe color space converter and enable */
sub_node = of_parse_phandle(drm->dev->of_node, "rgb2yuv", 0);
if (sub_node) {
crtc->rgb2yuv = xilinx_rgb2yuv_probe(drm->dev, sub_node);
of_node_put(sub_node);
if (IS_ERR(crtc->rgb2yuv)) {
DRM_ERROR("failed to probe a rgb2yuv\n");
return ERR_CAST(crtc->rgb2yuv);
}
}
/* probe a plane manager */
crtc->plane_manager = xilinx_drm_plane_probe_manager(drm);
if (IS_ERR(crtc->plane_manager)) {
DRM_ERROR("failed to probe a plane manager\n");
return ERR_CAST(crtc->plane_manager);
}
/* create a private plane. there's only one crtc now */
crtc->priv_plane = xilinx_drm_plane_create_private(crtc->plane_manager,
possible_crtcs);
if (IS_ERR(crtc->priv_plane)) {
DRM_ERROR("failed to create a private plane for crtc\n");
ret = PTR_ERR(crtc->priv_plane);
goto err_plane;
}
/* create extra planes */
xilinx_drm_plane_create_planes(crtc->plane_manager, possible_crtcs);
crtc->pixel_clock = devm_clk_get(drm->dev, NULL);
if (IS_ERR(crtc->pixel_clock)) {
DRM_DEBUG_KMS("failed to get pixel clock\n");
ret = -EPROBE_DEFER;
goto err_out;
}
ret = clk_prepare_enable(crtc->pixel_clock);
if (ret) {
DRM_DEBUG_KMS("failed to prepare/enable clock\n");
goto err_out;
}
sub_node = of_parse_phandle(drm->dev->of_node, "vtc", 0);
if (!sub_node) {
DRM_ERROR("failed to get a video timing controller node\n");
ret = -ENODEV;
goto err_out;
}
crtc->vtc = xilinx_vtc_probe(drm->dev, sub_node);
of_node_put(sub_node);
if (IS_ERR(crtc->vtc)) {
DRM_ERROR("failed to probe video timing controller\n");
ret = PTR_ERR(crtc->vtc);
goto err_out;
}
crtc->dpms = DRM_MODE_DPMS_OFF;
/* initialize drm crtc */
ret = drm_crtc_init(drm, &crtc->base, &xilinx_drm_crtc_funcs);
if (ret) {
DRM_ERROR("failed to initialize crtc\n");
goto err_out;
}
drm_crtc_helper_add(&crtc->base, &xilinx_drm_crtc_helper_funcs);
xilinx_drm_crtc_attach_property(&crtc->base);
return &crtc->base;
err_out:
xilinx_drm_plane_destroy_planes(crtc->plane_manager);
xilinx_drm_plane_destroy_private(crtc->plane_manager, crtc->priv_plane);
err_plane:
xilinx_drm_plane_remove_manager(crtc->plane_manager);
return ERR_PTR(ret);
}