void xio_init_usart(const uint8_t dev, // index into device array (ds)
const uint8_t offset, // index into USART array (us)
const uint32_t control,
const struct USART_struct *usart_addr,
const struct PORT_struct *port_addr,
const uint8_t dirclr,
const uint8_t dirset,
const uint8_t outclr,
const uint8_t outset)
{
// do all the bindings first (and in this order)
struct xioDEVICE *d = &ds[dev]; // setup device struct pointer
d->x = &us[offset]; // bind USART struct to device
struct xioUSART *dx = (struct xioUSART *)d->x; // setup USART struct pointer
dx->usart = (struct USART_struct *)usart_addr; // bind USART
dx->port = (struct PORT_struct *)port_addr; // bind PORT
// set flags
(void)xio_cntl(dev, control);// generic setflags -doesn't validate flags
if (EN_XOFF(d->flags) == TRUE) { // transfer flow control setting
dx->fc_state = FC_IN_XON; // resting state
}
// setup internal RX/TX buffers
dx->rx_buf_head = 1; // can't use location 0 in circular buffer
dx->rx_buf_tail = 1;
dx->tx_buf_head = 1;
dx->tx_buf_tail = 1;
// baud rate and USART setup
uint8_t baud = (uint8_t)(control & XIO_BAUD_gm);
if (baud == XIO_BAUD_UNSPECIFIED) {
baud = XIO_BAUD_DEFAULT;
}
xio_set_baud_usart(dev, baud); // usart must be bound first
dx->usart->CTRLB = (USART_TXEN_bm | USART_RXEN_bm);// enable tx and rx
dx->usart->CTRLA = CTRLA_RXON_TXON; // enable tx and rx IRQs
dx->port->DIRCLR = dirclr;
dx->port->DIRSET = dirset;
dx->port->OUTCLR = outclr;
dx->port->OUTSET = outset;
}
int xio_cntl_rs485(const uint32_t control) {return xio_cntl(XIO_DEV_RS485, control);}
int xio_cntl_pgm(const uint32_t control)
{
xio_cntl(XIO_DEV_PGM, control);
return (XIO_OK); // for now it's always OK
}
