code *orthxmm(elem *e, regm_t *pretregs)
{ elem *e1 = e->E1;
elem *e2 = e->E2;
regm_t retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
code *c = codelem(e1,&retregs,FALSE); // eval left leaf
unsigned reg = findreg(retregs);
regm_t rretregs = XMMREGS & ~retregs;
code *cr = scodelem(e2, &rretregs, retregs, TRUE); // eval right leaf
unsigned op = xmmoperator(e1->Ety, e->Eoper);
unsigned rreg = findreg(rretregs);
// float + ifloat is not actually addition
if ((e->Eoper == OPadd || e->Eoper == OPmin) &&
((tyreal(e1->Ety) && tyimaginary(e2->Ety)) ||
(tyreal(e2->Ety) && tyimaginary(e1->Ety))))
{
retregs |= rretregs;
c = cat(c, cr);
if (e->Eoper == OPmin)
{
unsigned nretregs = XMMREGS & ~retregs;
unsigned sreg; // hold sign bit
unsigned sz = tysize[tybasic(e1->Ety)];
c = cat(c,allocreg(&nretregs,&sreg,e2->Ety));
targ_size_t signbit = 0x80000000;
if (sz == 8)
signbit = 0x8000000000000000LL;
c = cat(c, movxmmconst(sreg, sz, signbit, 0));
c = cat(c, getregs(nretregs));
unsigned xop = (sz == 8) ? XORPD : XORPS; // XORPD/S rreg,sreg
c = cat(c, gen2(CNIL,xop,modregxrmx(3,rreg-XMM0,sreg-XMM0)));
}
if (retregs != *pretregs)
c = cat(c, fixresult(e,retregs,pretregs));
return c;
}
/* We should take advantage of mem addressing modes for OP XMM,MEM
* but we do not at the moment.
*/
code *cg;
if (OTrel(e->Eoper))
{
retregs = mPSW;
cg = NULL;
code *cc = gen2(CNIL,op,modregxrmx(3,rreg-XMM0,reg-XMM0));
return cat4(c,cr,cg,cc);
}
else
cg = getregs(retregs);
code *co = gen2(CNIL,op,modregxrmx(3,reg-XMM0,rreg-XMM0));
if (retregs != *pretregs)
co = cat(co,fixresult(e,retregs,pretregs));
return cat4(c,cr,cg,co);
}
code *orthxmm(elem *e, regm_t *pretregs)
{
//printf("orthxmm(e = %p, *pretregs = %s)\n", e, regm_str(*pretregs));
elem *e1 = e->E1;
elem *e2 = e->E2;
// float + ifloat is not actually addition
if ((e->Eoper == OPadd || e->Eoper == OPmin) &&
((tyreal(e1->Ety) && tyimaginary(e2->Ety)) ||
(tyreal(e2->Ety) && tyimaginary(e1->Ety))))
{
regm_t retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
unsigned reg;
regm_t rretregs;
unsigned rreg;
if (tyreal(e1->Ety))
{
reg = findreg(retregs);
rreg = findreg(retregs & ~mask[reg]);
retregs = mask[reg];
rretregs = mask[rreg];
}
else
{
// Pick the second register, not the first
rreg = findreg(retregs);
rretregs = mask[rreg];
reg = findreg(retregs & ~rretregs);
retregs = mask[reg];
}
assert(retregs && rretregs);
CodeBuilder cdb;
cdb.append(codelem(e1,&retregs,FALSE)); // eval left leaf
cdb.append(scodelem(e2, &rretregs, retregs, TRUE)); // eval right leaf
retregs |= rretregs;
if (e->Eoper == OPmin)
{
unsigned nretregs = XMMREGS & ~retregs;
unsigned sreg; // hold sign bit
unsigned sz = tysize(e1->Ety);
cdb.append(allocreg(&nretregs,&sreg,e2->Ety));
targ_size_t signbit = 0x80000000;
if (sz == 8)
signbit = 0x8000000000000000LL;
cdb.append(movxmmconst(sreg, sz, signbit, 0));
cdb.append(getregs(nretregs));
unsigned xop = (sz == 8) ? XORPD : XORPS; // XORPD/S rreg,sreg
cdb.gen2(xop,modregxrmx(3,rreg-XMM0,sreg-XMM0));
}
if (retregs != *pretregs)
cdb.append(fixresult(e,retregs,pretregs));
return cdb.finish();
}
regm_t retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
CodeBuilder cdb;
cdb.append(codelem(e1,&retregs,FALSE)); // eval left leaf
unsigned reg = findreg(retregs);
regm_t rretregs = XMMREGS & ~retregs;
cdb.append(scodelem(e2, &rretregs, retregs, TRUE)); // eval right leaf
unsigned rreg = findreg(rretregs);
unsigned op = xmmoperator(e1->Ety, e->Eoper);
/* We should take advantage of mem addressing modes for OP XMM,MEM
* but we do not at the moment.
*/
if (OTrel(e->Eoper))
{
retregs = mPSW;
cdb.gen2(op,modregxrmx(3,rreg-XMM0,reg-XMM0));
checkSetVex(cdb.last(), e1->Ety);
return cdb.finish();
}
else
cdb.append(getregs(retregs));
cdb.gen2(op,modregxrmx(3,reg-XMM0,rreg-XMM0));
checkSetVex(cdb.last(), e1->Ety);
if (retregs != *pretregs)
cdb.append(fixresult(e,retregs,pretregs));
return cdb.finish();
}
code *xmmpost(elem *e,regm_t *pretregs)
{
elem *e1 = e->E1;
elem *e2 = e->E2;
tym_t ty1 = tybasic(e1->Ety);
CodeBuilder cdb;
regm_t retregs;
unsigned reg;
bool regvar = FALSE;
if (config.flags4 & CFG4optimized)
{
// Be careful of cases like (x = x+x+x). We cannot evaluate in
// x if x is in a register.
unsigned varreg;
regm_t varregm;
if (isregvar(e1,&varregm,&varreg) && // if lvalue is register variable
doinreg(e1->EV.sp.Vsym,e2) // and we can compute directly into it
)
{
regvar = TRUE;
retregs = varregm;
reg = varreg; // evaluate directly in target register
cdb.append(getregs(retregs)); // destroy these regs
}
}
code cs;
if (!regvar)
{
code *c = getlvalue(&cs,e1,0); // get EA
cdb.append(c);
retregs = XMMREGS & ~*pretregs;
if (!retregs)
retregs = XMMREGS;
c = allocreg(&retregs,®,ty1);
cdb.append(c);
cs.Iop = xmmload(ty1, true); // MOVSD xmm,xmm_m64
code_newreg(&cs,reg - XMM0);
cdb.gen(&cs);
checkSetVex(cdb.last(), ty1);
}
// Result register
regm_t resultregs = XMMREGS & *pretregs & ~retregs;
if (!resultregs)
resultregs = XMMREGS & ~retregs;
unsigned resultreg;
code *c = allocreg(&resultregs, &resultreg, ty1);
cdb.append(c);
cdb.gen2(xmmload(ty1,true),modregxrmx(3,resultreg-XMM0,reg-XMM0)); // MOVSS/D resultreg,reg
checkSetVex(cdb.last(), ty1);
regm_t rretregs = XMMREGS & ~(*pretregs | retregs | resultregs);
if (!rretregs)
rretregs = XMMREGS & ~(retregs | resultregs);
c = codelem(e2,&rretregs,FALSE); // eval right leaf
cdb.append(c);
unsigned rreg = findreg(rretregs);
unsigned op = xmmoperator(e1->Ety, e->Eoper);
cdb.gen2(op,modregxrmx(3,reg-XMM0,rreg-XMM0)); // ADD reg,rreg
checkSetVex(cdb.last(), e1->Ety);
if (!regvar)
{
cs.Iop = xmmstore(ty1,true); // reverse operand order of MOVS[SD]
cdb.gen(&cs);
checkSetVex(cdb.last(), ty1);
}
if (e1->Ecount || // if lvalue is a CSE or
regvar) // rvalue can't be a CSE
{
cdb.append(getregs_imm(retregs)); // necessary if both lvalue and
// rvalue are CSEs (since a reg
// can hold only one e at a time)
cssave(e1,retregs,EOP(e1)); // if lvalue is a CSE
}
cdb.append(fixresult(e,resultregs,pretregs));
freenode(e1);
return cdb.finish();
}
code *xmmopass(elem *e,regm_t *pretregs)
{ elem *e1 = e->E1;
elem *e2 = e->E2;
tym_t ty1 = tybasic(e1->Ety);
unsigned sz1 = tysize[ty1];
regm_t rretregs = XMMREGS & ~*pretregs;
if (!rretregs)
rretregs = XMMREGS;
code *cr = codelem(e2,&rretregs,FALSE); // eval right leaf
unsigned rreg = findreg(rretregs);
code cs;
code *cl,*cg;
regm_t retregs;
unsigned reg;
bool regvar = FALSE;
if (config.flags4 & CFG4optimized)
{
// Be careful of cases like (x = x+x+x). We cannot evaluate in
// x if x is in a register.
unsigned varreg;
regm_t varregm;
if (isregvar(e1,&varregm,&varreg) && // if lvalue is register variable
doinreg(e1->EV.sp.Vsym,e2) // and we can compute directly into it
)
{ regvar = TRUE;
retregs = varregm;
reg = varreg; // evaluate directly in target register
cl = NULL;
cg = getregs(retregs); // destroy these regs
}
}
if (!regvar)
{
cl = getlvalue(&cs,e1,rretregs); // get EA
retregs = *pretregs & XMMREGS & ~rretregs;
if (!retregs)
retregs = XMMREGS & ~rretregs;
cg = allocreg(&retregs,®,ty1);
cs.Iop = xmmload(ty1); // MOVSD xmm,xmm_m64
code_newreg(&cs,reg - XMM0);
cg = gen(cg,&cs);
}
unsigned op = xmmoperator(e1->Ety, e->Eoper);
code *co = gen2(CNIL,op,modregxrmx(3,reg-XMM0,rreg-XMM0));
if (!regvar)
{
cs.Iop = xmmstore(ty1); // reverse operand order of MOVS[SD]
gen(co,&cs);
}
if (e1->Ecount || // if lvalue is a CSE or
regvar) // rvalue can't be a CSE
{
cl = cat(cl,getregs_imm(retregs)); // necessary if both lvalue and
// rvalue are CSEs (since a reg
// can hold only one e at a time)
cssave(e1,retregs,EOP(e1)); // if lvalue is a CSE
}
co = cat(co,fixresult(e,retregs,pretregs));
freenode(e1);
return cat4(cr,cl,cg,co);
}
